Susan L Downey

US Patent:

6614091, Sep 2, 2003

Filed:

Mar 13, 2002

Appl. No.:

10/097059

Inventors:

Susan H. Downey - Austin TX
James W. Miller - Austin TX
Geoffrey B. Hall - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2900

US Classification:

257499

Abstract:

An integrated circuit ( ) has a wire bond pad ( ). The wire bond pad ( ) is formed on a passivation layer ( ) over active circuitry ( ) and/or electrical interconnect layers ( ) of the integrated circuit ( ). The wire bond pad ( ) is connected to a plurality of final metal layer portions ( ). The plurality of final metal layer portions ( ) are formed in a final interconnect layer of the interconnect layers ( ). In one embodiment, the bond pad ( ) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad ( ) allows routing of conductors in a final metal layer ( ) directly underlying the bond pad ( ), thus allowing the surface area of the semiconductor die to be reduced.

US Patent:

6717270, Apr 6, 2004

Filed:

Apr 9, 2003

Appl. No.:

10/409766

Inventors:

Harold A. Downey - Austin TX
Susan H. Downey - Austin TX
James W. Miller - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2348

US Classification:

257758, 257779, 257784

Abstract:

An integrated circuit die includes an input/output (I/O) cell. The I/O cell includes active I/O circuitry in a substrate, a plurality of metal interconnect layers, an insulating layer, a first pad, and a second pad. The plurality of metal interconnect layers are formed over the substrate. The insulating layer is formed over the plurality of metal interconnect layers. The second pad is formed over the insulating layer and positioned directly over at least two metal structures in a final metal layer of the plurality of interconnect layers. The pad is selectively coupled to one of at least two metal structures by at least one opening in the insulating layer.

US Patent:

6846717, Jan 25, 2005

Filed:

Jun 24, 2003

Appl. No.:

10/606674

Inventors:

Susan H. Downey - Austin TX, US
James W. Miller - Austin TX, US
Geoffrey B. Hall - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 2176

US Classification:

438400, 438618

Abstract:

An integrated circuit () has a wire bond pad (). The wire bond pad () is formed on a passivation layer () over active circuitry () and/or electrical interconnect layers () of the integrated circuit (). The wire bond pad () is connected to a plurality of final metal layer portions (). The plurality of final metal layer portions () are formed in a final interconnect layer of the interconnect layers (). In one embodiment, the bond pad () is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad () allows routing of conductors in a final metal layer () directly underlying the bond pad (), thus allowing the surface area of the semiconductor die to be reduced.

US Patent:

6921979, Jul 26, 2005

Filed:

Nov 26, 2002

Appl. No.:

10/304416

Inventors:

Susan H. Downey - Austin TX, US
Peter R. Harper - Round Rock TX, US
Kevin Hess - Austin TX, US
Michael V. Leoni - Austin TX, US
Tu-Anh Tran - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L023/48
H01L023/52
H01L029/40

US Classification:

257773, 257779, 257780, 257781, 257784, 257786

Abstract:

A bond pad () has a first wire bond region () and a second wire bond region (). In one embodiment, the first wire bond region () extends over a passivation layer (). In an alternate embodiment, a bond pad () has a probe region (), a first wire bond region (), and a second wire bond region (). In one embodiment, the probe region () and the wire bond region () extend over a passivation layer (). The bond pads may have any number of wire bond and probe regions and in any configuration. The ability for the bond pads to have multiple wire bond regions allows for multiple wire connections to a single bond pad, such as in multi-chip packages. The ability for the bond pads to extend over the passivation layer also allows for reduced integrated circuit die area.

US Patent:

6998952, Feb 14, 2006

Filed:

Dec 5, 2003

Appl. No.:

10/729531

Inventors:

Yaping Zhou - Austin TX, US
Susan H. Downey - Austin TX, US
Sheila F. Chopin - Austin TX, US
Tu-Anh Tran - Austin TX, US
Alan H. Woosley - Austin TX, US
Peter R. Harper - Lucas TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01F 27/06
H01F 5/00

US Classification:

336200, 336232, 336192, 336 65, 296021

Abstract:

An inductive device () is formed above a substrate () having a conductive coil formed around a core (). The coil comprises segments formed from a first plurality of bond wires () and a second plurality of bond wires (). The first plurality of bond wires () extends between the core () and the substrate (). Each of the first plurality of bond wires is coupled to two of a plurality of wire bond pads (). The second plurality of bond wires () extends over the core () and is coupled between two of the plurality of wire bond pads (). A shield () includes a portion that is positioned between the core () and the substrate ().

US Patent:

7015585, Mar 21, 2006

Filed:

Dec 18, 2002

Appl. No.:

10/323296

Inventors:

Susan H. Downey - Austin TX, US
Sheila F. Chopin - Austin TX, US
Peter R. Harper - Round Rock TX, US
Sohrab Safai - Round Rock TX, US
Tu-Anh Tran - Austin TX, US
Alan H. Woosley - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/48

US Classification:

257774, 257773, 257776, 257662, 257663, 257690, 257678, 257786

Abstract:

An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.

US Patent:

7138328, Nov 21, 2006

Filed:

May 18, 2004

Appl. No.:

10/847775

Inventors:

Susan H. Downey - Austin TX, US
Peter R. Harper - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/44
H01L 29/40
B23K 31/00

US Classification:

438617, 438106, 2281791, 228904, 257784

Abstract:

A packaged IC including insulated wire for electrically connecting conductive structures of the packaged IC. In some embodiments, the packaged IC includes an IC die attached to a package substrate, where bond pads of the IC die are electrically connected to bond fingers of the substrate with insulated wire. The insulated wire has a conductive core and an insulator coating. In some examples, the insulator coating includes an inorganic covalently-bonded substance that is not an oxide of the electrically conductive core such as, e. g. , silicon nitride or silicon oxide. In one example, the insulator coating is applied to a conductive core by a chemical vapor deposition (CVD) process such as a plasma enhanced chemical vapor deposition (PECVD).

US Patent:

7241636, Jul 10, 2007

Filed:

Jan 11, 2005

Appl. No.:

11/033008

Inventors:

Kevin J. Hess - Austin TX, US
Susan H. Downey - Austin TX, US
James W. Miller - Austin TX, US
Cheng Choi Yong - Kuala Lumpur, MY

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R 31/26
H01L 21/66

US Classification:

438 14, 257E21525

Abstract:

A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.