Susan F Walker

US Patent:

8457698, Jun 4, 2013

Filed:

Jan 5, 2011

Appl. No.:

12/984932

Inventors:

Dragan M. Samardzija - Highlands NJ, US
Cuong Tran - Howell NJ, US
Howard C. Huang - New York NY, US
Susan J. Walker - Freehold NJ, US
Reinaldo A. Valenzuela - Holmdel NJ, US

Assignee:

Alcatel Lucent - Paris

International Classification:

H04M 1/00

US Classification:

4555757, 455 631, 455 69, 4555521, 455561, 4555621

Abstract:

The present invention relates to an antenna array for supporting multiple beam architectures. For example, a transceiver may include an antenna array. The antenna array includes a plurality of antenna elements, where the plurality of antenna elements is configured to support at least two beam architectures in a cell site. Each beam architecture is associated with a different configuration of sectors and beamforming signals. According to one embodiment, each beam architecture is associated with a different wireless standard. According to another embodiment, each beam architecture is associated with a different carrier within one wireless standard. The antenna elements may be arranged as a circular array.

US Patent:

20100247278, Sep 30, 2010

Filed:

Mar 31, 2009

Appl. No.:

12/415064

Inventors:

Eric C. Beck - Colts Neck NJ, US
Theodore Sizer - Littlel Silver NJ, US
Cuong Tran - Howell NJ, US
Susan J. Walker - Freehold NJ, US

International Classification:

B60P 1/00

US Classification:

414467

Abstract:

An apparatus and method for deploying a payload at a location are provided. The apparatus includes a mount adapted to be attached to a mobile unit while allowing normal operation of the mobile unit, and a deployment mechanism. The deployment mechanism supports a payload securing mode in which the deployment mechanism secures the payload to the mount and a payload deployment mode in which the deployment mechanism causes the payload to be ejected from the mount. The deployment mechanism is adapted to transition from the payload securing mode to the payload deployment mode in response to a control signal. The deployment mechanism includes a securing means adapted for securing the payload to the mount, an ejecting means adapted for ejecting the payload from the mount, and a breaking means adapted for breaking the securing means in response to a control signal, thereby causing the ejecting means to eject the payload from the mount.

US Patent:

59146338, Jun 22, 1999

Filed:

Aug 8, 1997

Appl. No.:

8/906912

Inventors:

Vittorio Comino - Keansburg NJ
Dima David Shulman - Marlboro NJ
Susan Jeanne Walker - Howell NJ

Assignee:

Lucent Technologies Inc.

International Classification:

H03K 500
H03M 112

US Classification:

327553

Abstract:

A tuning circuit for generating a digital code to be used to calibrate a capacitor array of the type used in active RC filters is comprised of a single-slope A/D converter with fixed reference voltages as inputs and an output value which is dependent on the RC product of a resistor and capacitor within the converter. A decoder converts the RC product as measured by the A/D converter into a digital code which, when applied to the appropriate capacitor array, sets the array capacitance to compensate for the difference between the measured RC product and the nominal design value.

US Patent:

58776451, Mar 2, 1999

Filed:

Aug 8, 1997

Appl. No.:

8/908573

Inventors:

Vittorio Comino - Keansburg NJ
Dima David Shulman - Marlboro NJ
Susan Jeanne Walker - Howell NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H03G 1108
H03L 500

US Classification:

327350

Abstract:

A circuit for compensating for the input offset voltage of a logarithmic amplifier includes a digital comparator, a logic circuit, and a digital-to-analog converter (DAC) in a feedback loop. The comparator is connected to the output of the log amplifier and digitally indicates the polarity of the input offset voltage when the amplifier input is set to zero. The logic circuit uses the digital output of the comparator to form an adjustable digital compensation signal. This digital compensation signal is applied to the DAC to generate an analog compensation signal that is injected into the input of the logarithmic amplifier to cancel the input offset voltage. The process is repeated until the proper or best compensation signal is produced.