Syed Hasan Yousuf

US Patent:

7138792, Nov 21, 2006

Filed:

Oct 25, 2004

Appl. No.:

10/972892

Inventors:

Zhenhai Fu - Fremont CA, US
Syed Hasan Yousuf - Saratoga CA, US
Philip N. Alex - San Jose CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 31/02
G01R 31/00
G06F 1/28

US Classification:

3241581, 324763, 324754, 713340

Abstract:

An apparatus for routing power between a set of power supply taps of an automated tester and power connections on an integrated circuit under test, where the integrated circuit belongs to a family of integrated circuits that have a common power connection layout and different power connection voltage requirements. An interface board having first electrical contacts disposed in the common power connection layout makes electrical connections to the power connections of all integrated circuits belonging to the family of integrated circuits. The first electrical contacts are electrically routed to second electrical contacts disposed in a standardized configuration. A power personality card having third electrical contacts makes electrical connections to the second electrical contacts of the interface board. Fourth electrical contacts are disposed in a standardized configuration, and the third electrical contacts are electrically routed to the fourth electrical contacts via electrical lines that are hard wired for the power connection voltage requirements of the integrated circuit under test. The power personality card and the interface board are interchangeable, one with another.

US Patent:

61287571, Oct 3, 2000

Filed:

Jun 16, 1998

Appl. No.:

9/098172

Inventors:

Syed Hasan Yousuf - Saratoga CA
Veronica Collaco Stewart - San Jose CA
Hai Xuan Nguyen - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3128

US Classification:

714724

Abstract:

A method for improving the fault coverage of functional tests for integrated circuits by establishing a design-specific low voltage functional screening procedure. In the disclosed embodiment of the invention, a reduced voltage test threshold is established by comparing the results of an iterative test procedure executed on a set of known good integrated circuits and integrated circuits which have passed traditional functional test programs but manifested problems in the field. For a given device under test, the iterative procedure commences by applying a system clock and nominal power supply voltage. A set of functional test vectors is then executed on the device using automated test equipment (ATE). The results are compared with expected test results to determine if the device is a passing device under the initial test conditions. If so, the power supply voltage is decremented by a predetermined value and the test process is repeated.