Tak Shun Wong

US Patent:

7747828, Jun 29, 2010

Filed:

Nov 17, 2004

Appl. No.:

10/992428

Inventors:

Yunsheng Wang - San Jose CA, US
Casey Springer - Portland OR, US
Tak Kwong Wong - Milpitas CA, US
Bill Beane - Gustine CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

G06F 13/20

US Classification:

711149, 711147, 711131, 711154

Abstract:

A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.

US Patent:

7904667, Mar 8, 2011

Filed:

Aug 10, 2006

Appl. No.:

11/503431

Inventors:

Yunsheng Wang - San Jose CA, US
Casey Springer - Portland OR, US
Tak Kwong Wong - Milpitas CA, US
Bill Beane - Gustine CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

G06F 13/20

US Classification:

711149, 711101, 711131, 711154

Abstract:

A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.

US Patent:

60697822, May 30, 2000

Filed:

Aug 26, 1998

Appl. No.:

9/140619

Inventors:

Chuen-Der Lien - Los Altos Hills CA
Tak Kwong Wong - Milpitas CA

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

H02H 900

US Classification:

361111

Abstract:

A circuit for protecting the internal circuitry of a semiconductor chip from increased power supply voltages due to electrostatic discharge events is presented. The circuit comprises a trigger circuit including a resistor and diode array coupled between a power line and a ground line and a discharge circuit which, when turned on by an output signal of the trigger circuit, conducts the excess charge on the power line to ground.

US Patent:

20210256669, Aug 19, 2021

Filed:

Apr 7, 2021

Appl. No.:

17/224830

Inventors:

- Cupertino CA, US
Alok Deshpande - Mountain View CA, US
Anita Nariani Schulze - Los Altos CA, US
Hao Sun - San Jose CA, US
Jun Hu - Sunnyvale CA, US
Morten Poulsen - Palo Alto CA, US
Tak Shing Wong - Pleasanton CA, US
Wu Cheng - Millbrae CA, US

International Classification:

G06T 5/00
G06K 9/46
H04N 5/235

Abstract:

Devices, methods, and computer-readable media are disclosed describing an adaptive approach for image bracket selection and fusion, e.g., to generate low noise and high dynamic range (HDR) images in a wide variety of capturing conditions. An incoming image stream may be obtained from an image capture device, wherein the incoming image stream comprises a variety of differently-exposed captures, e.g., EV images, EV− images, EV+ images, long exposure (or synthetic long exposure) images, EV/EV− image pairs, etc., which are received according to a particular pattern. When a capture request is received, a set of rules and/or a decision tree may be used to evaluate one or more capture conditions associated with the images from the incoming image stream and determine which two or more images to select for a fusion operation. A noise reduction process may optionally be performed on the selected images before (or after) the registration and fusion operations.

US Patent:

20190370948, Dec 5, 2019

Filed:

May 30, 2019

Appl. No.:

16/426448

Inventors:

- Cupertino CA, US
Alok Deshpande - Mountain View CA, US
Anita Nariani Schulze - Los Altos CA, US
Hao Sun - San Jose CA, US
Jun Hu - Sunnyvale CA, US
Morten Poulsen - Palo Alto CA, US
Tak Shing Wong - Pleasanton CA, US
Wu Cheng - Millbrae CA, US

International Classification:

G06T 5/00
G06K 9/46
H04N 5/235

Abstract:

Devices, methods, and computer-readable media are disclosed describing an adaptive approach for image bracket selection and fusion, e.g., to generate low noise and high dynamic range (HDR) images in a wide variety of capturing conditions. An incoming image stream may be obtained from an image capture device, wherein the incoming image stream comprises a variety of differently-exposed captures, e.g., EV0 images, EV− images, EV+ images, long exposure (or synthetic long exposure) images, EV0/EV− image pairs, etc., which are received according to a particular pattern. When a capture request is received, a set of rules and/or a decision tree may be used to evaluate one or more capture conditions associated with the images from the incoming image stream and determine which two or more images to select for a fusion operation. A noise reduction process may optionally be performed on the selected images before (or after) the registration and fusion operations.

US Patent:

20170256035, Sep 7, 2017

Filed:

Mar 1, 2016

Appl. No.:

15/057945

Inventors:

- TOKYO, JP
TAK SHING WONG - FREMONT CA, US
XIAOGANG DONG - BOYDS MD, US

International Classification:

G06T 5/00
G06T 7/40
G06T 7/00
G06K 9/46
G06K 9/62
G06K 9/52

Abstract:

A method for processing a multi-channel image includes modification of adjusted pixel values of one or more pixels in a region of the multi-channel image, in accordance with a pre-specified signal pattern based on one or more parameters. A score is determined based on a ratio of a pixel difference value and a maximum pixel step value. The maximum pixel step value corresponds to modified pixel values of the one or more pixels in the region when the maximum pixel step value exceeds a threshold noise level for the region. False color is suppressed in a selected region of the multi-channel image based on the determined score when the false color is identified in the region.

US Patent:

20160284066, Sep 29, 2016

Filed:

Mar 26, 2015

Appl. No.:

14/669433

Inventors:

- Tokyo, JP
Jiro Takatori - Tokyo, JP
Tak Shing Wong - FREMONT CA, US

International Classification:

G06T 5/00
H04N 5/235
G06T 15/50
G06T 7/20
G06T 3/00
G06T 5/50
H04N 9/04

Abstract:

A method to improve video quality by suppressing noise and artifacts in difference frames of a video is described herein.

US Patent:

20160205331, Jul 14, 2016

Filed:

Jan 9, 2015

Appl. No.:

14/593133

Inventors:

- Tokyo, JP
HIROAKI EBI - Tokyo, JP
JIRO TAKATORI - Cupertino CA, US
ALEXANDER BERESTOV - San Jose CA, US
KENICHI NISHIO - Kanagawa, JP
TAK SHING WONG - Fremont CA, US

International Classification:

H04N 5/357
H04N 13/02
H04N 5/235

Abstract:

Various aspects of a method and a system for image processing are disclosed herein. The method includes processing an input image, which comprises structure information and detail information, using image processing (IP) blocks in an image processing pipeline. One or more of the IP blocks, such as the “lossy” IP blocks, process the input image with at least a partial loss of the detail information. By replacing the “lossy” IP blocks with redesigned image processing (IP) modules, the image processing pipeline reduces or avoids such loss of the detail information. A more efficient implementation of the improved pipeline is realized by using a master IP module when the “lossy” IP blocks are reordered and grouped together in the image processing pipeline. The method is further extended to process 3-D images to reduce or avoid loss of detail information in a 3-D image processing pipeline.