Tam M Bui

US Patent:

6717594, Apr 6, 2004

Filed:

Sep 25, 2000

Appl. No.:

09/668549

Inventors:

Tam D. Bui - Austin TX
George John Dawkins - Austin TX
Van Hoa Lee - Cedar Park TX
Jayeshkumar M. Patel - Austin TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06T 1500

US Classification:

345763, 345501, 345522, 345965, 709221, 709222, 713 1, 713 2

Abstract:

A data processing system and method are disclosed for displaying a graphical depiction of the system configuration of the data processing system. Execution of a boot process of the data processing system is started. Prior to a completion of the boot process, a configuration of the data processing system is determined by the system itself. A graphical depiction of the configuration is then generated. The graphical depiction is then graphically displayed utilizing a display screen which is included in the data processing system. The graphical depiction illustrates each device included in the system as well as how the devices are interconnected. Thereafter, the execution of the boot process is completed. The steps of determining a configuration, generating a graphical depiction, and graphically displaying the graphical depiction are completed prior to completing the booting the data processing system, and thus prior to an operating system being executed by the data processing system.

US Patent:

6745269, Jun 1, 2004

Filed:

Jan 11, 2001

Appl. No.:

09/758736

Inventors:

Tam D. Bui - Austin TX
George John Dawkins - Austin TX
Van Hoa Lee - Cedar Park TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710104, 713 1, 713 2, 713100

Abstract:

A method and apparatus preserve the data structures established in the earliest stage of initial power load, rather than each system firmware component rediscovering the hardware components of the system. Thus, the data structure is available at later stages for other firmware components. In a logical partitioning machine, the open firmware partition manager can utilize the data structure to support the partitions open firmware device tree construction. The partition manager customizes the copies of these data structures residing in the partitions memory. For hardware devices in the system but not belonging to the partition, the device information is cleared and marked invalid. After the data structures are established and updated by the earliest firmware I/O configuration component, the addresses of these structures are provided to the open firmware component. The open firmware copies these data structures to its internally safe working area and uses the copies for its normal operation. When runtime abstraction service firmware component is instantiated, the addresses of the structures of open firmwares copies are provided by the open firmware component to runtime abstraction service.

US Patent:

6957252, Oct 18, 2005

Filed:

Oct 12, 2000

Appl. No.:

09/687099

Inventors:

Tam D. Bui - Austin TX, US
Chetan Mehta - Austin TX, US
Keng-Hiup Ng - Kuala Lumpur, MY
Jayeshkumar M. Patel - Ausitn TX, US
Amir Simon - Austin TX, US
Kiet Anh Tran - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F015/16

US Classification:

709220, 709221

Abstract:

A method, system, and apparatus for synchronizing device, node, and drawer addresses between two networks within a data processing system is provided. In one embodiment, a service processor assigns a plurality of SPCN addresses to each of a plurality of devices in the data processing system. System firmware then determines the RIO addresses corresponding to the plurality of devices. If one of the SPCN addresses is not the same as the RIO address for the corresponding device, node, or drawer, then the service processor reassigns a new SPCN address to the corresponding device, node, or drawer such that the new SPCN address is identical to the RIO address for a corresponding device, node, or drawer.

US Patent:

6961785, Nov 1, 2005

Filed:

Aug 3, 2000

Appl. No.:

09/631723

Inventors:

Richard Louis Arndt - Austin TX, US
Tam D. Bui - Austin TX, US
Van Hoa Lee - Cedar Park TX, US
David Lee Randall - Leander TX, US
Kiet Anh Tran - Cedar Park TX, US
David R. Willoughby - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F003/00
G06F013/00

US Classification:

710 9, 710104, 710302, 713 1

Abstract:

A system for managing input/output drawers within a data processing system. A unique identifier is assigned to each of a plurality of drawers, and is used by the operating system to identify the drawers in the system regardless of how these drawers are interconnected. Another unique PCI-bridge identifier is assigned to each of a plurality of PCI Host bridges (PHBs) from all drawers, and is used by the operating system to perform input/output processes to devices associated with the plurality of PHBs such that the ODM object for each of the PHBs remains the same regardless of how the drawer is interconnected in the system. When a new drawer is added to the system, a new unique identifier is assigned to the new drawer ensuring that the unique identifiers previously assigned to the other drawers are not used to identify the new drawer.

US Patent:

6658594, Dec 2, 2003

Filed:

Jul 13, 2000

Appl. No.:

09/616142

Inventors:

Tam D. Bui - Austin TX
Van Hoa Lee - Cedar Park TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 10, 714 9, 714 57, 712 16

Abstract:

A method, system, and apparatus of recording information generated by a data processing system prior to completion enablement of programmed input/output services for the data processing system is provided. In one embodiment, a service processor receives an attention interrupt from a host processor. The service processor then stops the operation of all host processors in the data processing system. The service processor then reads the information, such as a system checkpoint, from a buffer within the host processors system memory and writes the information into a non-volatile random access memory as well as displays the information to a user via a video display. The service processor then restarts the host processors.