Tam T Tran

US Patent:

6515910, Feb 4, 2003

Filed:

Feb 15, 2002

Appl. No.:

10/076826

Inventors:

Peter W. Lee - Saratoga CA
Hsing-Ya Tsao - San Jose CA
Tam Tran - San Jose CA
Fu-Chang Hsu - San Jose CA

Assignee:

Aplus Flash Technology Inc. - San Jose CA

International Classification:

G11C 1606

US Classification:

36518522, 36518529, 3651853, 36518509

Abstract:

A method to test the erase condition of memory cells in a memory array device is achieved. The method is further extended to methods to detect and correct under erase and over erase conditions. The erase condition of a section of the memory array device is altered to form an erased section and non-erased sections. The control gates of the memory cells in the non-erased sections are forced to a normal off-state voltage sufficient to turn off erased cells. The control gates of the memory cells in non-selected subsections of the erased section are forced to a guaranteed off-state voltage that will turn off erased cells including those that are over erased. The control gates of the memory cells in a selected subsection of the erased section are forced to a check voltage. Thereafter, the bitline current of the selected subsection of the erased section is measured to determine erase condition of the selected subsection of the erase section.

US Patent:

6563742, May 13, 2003

Filed:

Mar 4, 2002

Appl. No.:

10/090356

Inventors:

Peter W. Lee - Saratoga CA
Tam H. Tran - San Jose CA

Assignee:

Aplus Flash Technology, Inc. - San Jose CA

International Classification:

G11C 1600

US Classification:

36518529, 365 63, 36518522

Abstract:

A multiple time programmable (MTP) memory device is achieved. The device comprises, first, a memory cell array including a means of electrical erasability and electrical programmability. The memory cell array comprises, preferably, a Flash memory cell array. A package has an external pin configuration that conforms to the JEDEC standard for an EPROM device wherein an external, positive programming voltage (VPP) pin is provided. Finally, an external, negative erasing voltage (VNN) pin is provided. The VNN pin is, preferably, multiplexed with the chip enable bar (CEB) pin.

US Patent:

6943617, Sep 13, 2005

Filed:

Dec 29, 2003

Appl. No.:

10/748540

Inventors:

Hieu Van Tran - San Jose CA, US
Tam Huu Tran - San Jose CA, US
Vishal Sarin - Santa Clara CA, US
Anh Ly - San Jose CA, US
Niang Hangzo - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G05F001/10

US Classification:

327539

Abstract:

A bandgap reference generator comprises a PMOS transistor and NMOS transistor in a pnp bipolar junction transistor connected in series in a first leg. The bandgap reference generator includes a second leg that includes a PMOS transistor, an NMOS transistor, a resistor and a pnp bipolar junction transistor. A bias circuit provides a bias to a mirror formed by the gates of the PMOS transistors to lower the operating voltage of the bandgap reference generator. A second biasing circuit may provide bias to the mirror formed of the NMOS transistors. A time-based and a DC bias-based start up circuitry and method is provided.

US Patent:

7454634, Nov 18, 2008

Filed:

Mar 2, 2005

Appl. No.:

11/070481

Inventors:

Timothy Donovan - Livermore CA, US
Shafiq Jamal - Gilroy CA, US
Yonghua Song - Cupertino CA, US
Chia-Chun Chung - San Jose CA, US
Tam Tran - San Ramon CA, US
Lawrence Tse - Fremont CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 1/32

US Classification:

713322, 713323

Abstract:

A wireless network device having active and inactive modes comprises a clock generating module that generates a first clock signal having a first clock rate. A voltage supply module generates a first voltage level and a second voltage level that is less than the first voltage level. A first digital module receives the first clock rate and the first voltage level during the active mode, receives the second voltage level during the inactive mode and does not receive the first clock signal during the inactive mode. A first analog module communicates with the voltage supply module and has reduced current consumption during the inactive mode.

US Patent:

8050200, Nov 1, 2011

Filed:

Oct 3, 2007

Appl. No.:

11/866754

Inventors:

Sandesh Goel - Fremont CA, US
Timothy J. Donovan - Livermore CA, US
Ken Kinwah Ho - San Jose CA, US
Yungping Hsu - Saratoga CA, US
Kedar Shirali - Sunnyvale CA, US
Atul Salhotra - Sunnyvale CA, US
Tam Tran - San Ramon CA, US
Chia-Chun Chung - San Jose CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H04B 1/44
G06F 11/00
H04L 12/43

US Classification:

370282, 370229, 370445

Abstract:

A system includes a signal processing module and a control module. The signal processing module receives a first clear channel assessment (CCA) signal for a first sub-channel of a communication channel, increases a pulse width of the first CCA signal by a predetermined period of time, and generates a second CCA signal. The control module receives the second CCA signal and a third CCA signal for a second sub-channel of the communication channel. The control module transmits data via one of the second sub-channel and the communication channel based on the second and third CCA signals.

US Patent:

8441967, May 14, 2013

Filed:

Oct 24, 2011

Appl. No.:

13/279520

Inventors:

Sandesh Goel - Fremont CA, US
Timothy J. Donovan - Livermore CA, US
Ken Kinwah Ho - San Jose CA, US
Yungping Hsu - Saratoga CA, US
Kedar Shirali - Sunnyvale CA, US
Atul Salhotra - Sunnyvale CA, US
Tam Tran - San Ramon CA, US
Chia-Chun Chung - San Jose CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H04B 1/44
G06F 11/00
H04L 12/43

US Classification:

370282, 370229, 370445

Abstract:

A system includes a signal processing module and a control module. The signal processing module receives a first clear channel assessment (CCA) signal for a first sub-channel of a communication channel, increases a pulse width of the first CCA signal by a predetermined period of time, and generates a second CCA signal. The control module receives the second CCA signal and a third CCA signal for a second sub-channel of the communication channel. The control module transmits data via one of the second sub-channel and the communication channel based on the second and third CCA signals.

US Patent:

7995543, Aug 9, 2011

Filed:

May 5, 2006

Appl. No.:

11/429633

Inventors:

Ken Kinwah Ho - San Jose CA, US
Tam Tran - San Ramon CA, US
Chia-Chun Chung - San Jose CA, US
Timothy J. Donovan - Livermore CA, US
Sonali Bagchi - San Jose CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H04W 4/00

US Classification:

370338, 370328

Abstract:

A wireless network device includes N access point (AP) modules having N BSSID's, where N is an integer greater than 1. The wireless network device includes a control module that communicates with the N AP modules. The control module stores the N BSSID's, a BSSID of an (N+1)external AP that communicates with M client stations, and at least one MAC address of at least one of the M client stations, where M is an integer greater than or equal to 1. The control module communicates with the (N+1)external AP by emulating at least one of the M client stations.

US Patent:

20070027837, Feb 1, 2007

Filed:

Jul 28, 2005

Appl. No.:

11/190947

Inventors:

Marcel Kutsch - Koeln, DE
Volker Markl - San Jose CA, US
Nimrod Megiddo - Palo Alto CA, US
Tam Minh Tran - San Jose CA, US

International Classification:

G06F 17/30

US Classification:

707002000

Abstract:

A method for consistent selectivity estimation based on the principle of maximum entropy (ME) is provided. The method efficiently exploits all available information and avoids the bias problem. In the absence of detailed knowledge, the ME approach reduces to standard uniformity and independence assumptions. The disclosed method, based on the principle of ME, is used to improve the optimizer's cardinality estimates by orders of magnitude, resulting in better plan quality and significantly reduced query execution times.