Tan Nhat Tran

US Patent:

7254667, Aug 7, 2007

Filed:

Apr 2, 2004

Appl. No.:

10/815982

Inventors:

Tan Ba Tran - Round Rock TX, US
Richard Roy Grisenthwaite - Cambridgeshire, GB
Gerard Richard Williams - Sunset Valley TX, US

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 12/00

US Classification:

711100, 712215, 711105

Abstract:

A data processor core comprising a memory access interface portion operable to perform data transfer operations between an external data source and at least one memory associated with said data processor core and a data processing portion operable to perform further data processing operations in response to receipt of said processor clock signal CLK. The two portions of the core being operable to be independently enabled such that one portion may be active while the other is inactive.

US Patent:

20050223129, Oct 6, 2005

Filed:

Apr 2, 2004

Appl. No.:

10/815961

Inventors:

Tan Tran - Round Rock TX, US
Gerard Williams - Sunset Valley TX, US
David Matheny - Austin TX, US
David Flynn - Cambridge, GB

Assignee:

ARM LIMITED - Cambridge

International Classification:

G06F013/28

US Classification:

710022000, 711158000

Abstract:

A data processor core comprising: a memory access interface portion operable to perform data transfer operations between an external data source and at least one memory associated with said data processor core; a data processing portion operable to perform data processing operations; a read/write port operable to transfer data from said processor core to at least two buses A, B said at least two buses being operable to provide data communication between said processor core and said at least one memory , said at least one memory comprising at least two portions A, B, each of said at least two buses A, B being operable to provide data access to respective ones of said at least two portions A, B; arbitration logic associated with said read/write port ; wherein said arbitration logic is operable to route a data access request requesting access of data in one portion of said at least one memory received from said memory access interface to one of said at least two buses providing access to said one portion of said at least one memory and to route a further data access request requesting access of data in a further portion of said at least one memory received from said data processing portion to a further one of said at least two buses providing access to said further portion of said at least one memory, said routing of said data access requests being performed during the same clock cycle.

Address:

17119 Burrowdale Ct, Houston, TX 77084

Phone:

(832)6383365

VIN:

4T1BF1FK3CU619786

Make:

TOYOTA

Model:

CAMRY

Year:

2012