Theodoros G Mihopoulos

US Patent:

6528377, Mar 4, 2003

Filed:

Feb 10, 2000

Appl. No.:

09/501950

Inventors:

Theodoros Mihopoulos - Austin TX
Prasad V. Alluri - Austin TX
J. Vernon Cole - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21331

US Classification:

438311, 438151, 438154, 438312, 438322

Abstract:

A silicon-on-insulator substrate and its method of formation are disclosed. In another embodiment, a method for forming a high-k gate dielectric is disclosed. The silicon-on-insulator substrate is prepared by forming a lattice matched dielectric layer ( ) over a semiconductor substrate ( ). A thermodynamically stable dielectric layer ( ) is then formed over the lattice matched dielectric layer ( ). A semiconductor layer ( ) is then formed over the thermodynamically stable dielectric layer ( ). Formation of the high-k gate dielectric includes the processing steps used to form the silicon-on-insulator substrate and additionally includes bonding a second semiconductor substrate ( ) to the semiconductor layer ( ). The first semiconductor substrate ( ) is then removed to expose the lattice matched dielectric layer ( ). This results in a silicon substrate that has a layer of high-k dielectric material that can be used as the gate dielectric for integrated circuits formed on the substrate.

US Patent:

20170040517, Feb 9, 2017

Filed:

Oct 18, 2016

Appl. No.:

15/296935

Inventors:

- Eindhoven, NL
Mark Melvin Butterworth - San Jose CA, US
Theodoros Mihopoulos - San Jose CA, US

International Classification:

H01L 33/62
H01L 33/46
H01L 33/40
H01L 33/38

Abstract:

Embodiments of the invention include a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A metal n-contact is connected to the n-type region. A metal p-contact is in direct contact with the p-type region. An interconnect is electrically connected to one of the n-contact and the p-contact. The interconnect is disposed adjacent to the semiconductor structure.

US Patent:

20160093775, Mar 31, 2016

Filed:

Apr 10, 2014

Appl. No.:

14/786522

Inventors:

- Eindhoven, NL
Mark Melvin Butterworth - San Jose CA, US
Theodoros Mihopoulos - San Jose CA, US

International Classification:

H01L 33/38
H01L 33/50
H01L 33/62
H01L 33/46

Abstract:

Embodiments of the invention include a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A metal n-contact is connected to the n-type region. A metal p-contact is in direct contact with the p-type region. An interconnect is electrically connected to one of the n-contact and the p-contact. The interconnect is disposed adjacent to the semiconductor structure.