Tegze Peter Haraszti

US Patent:

56129645, Mar 18, 1997

Filed:

Apr 8, 1991

Appl. No.:

7/681600

Inventors:

Tegze P. Haraszti - Newport Beach CA

International Classification:

G11C 1900
G11C 2100
G11C 2900

US Classification:

371 401

Abstract:

A high performance fault tolerant orthogonal shuffle memory comprising a plurality of memory cells arranged to form a two-dimensional array of rows and columns. Each memory cell includes a data store element for storing data and a multi-state data transmission element to provide access to the data stored in the data store element. Each memory cell has the dual function of storing and transmitting (i. e. shifting) data. The memory cell array is coupled to first and second registers and a shuffle signal generator. In operation, data is shuffled column by column through the array, such that only two columns of memory cells are activated at any time. The shuffle memory herein disclosed may form subarrays of each of a data storage array and a redundancy storage array that are coupled to an improved error detector and corrector to form a high performance fault tolerant orthogonal memory system.

US Patent:

47792264, Oct 18, 1988

Filed:

Dec 29, 1986

Appl. No.:

6/946795

Inventors:

Tegze P. Haraszti - Newport Beach CA

International Classification:

G11C 1500
G11C 1100
G11C 700

US Classification:

365 49

Abstract:

Static content addressable memory cells (CAMs) combining six transistors and two pairs of control signal lines, where both pairs of lines provide dual functions and where the content addressing function is provided by a unique combination of control and precharge signals on the four control signal lines. An alternate CAM embodiment comprising eight transistors and an additional interrogation signal line is also disclosed. The disclosed content addressable memory cells are preferably implemented by complementary metal oxide field effect transistors (CMOSFETs) and have particular application in very large scale integrated (VLSI) chips, where small cell size is of high importance and/or where high operational speed, reliability, radiation hardness and/or noise immunity, and/or operation at high temperatures and/or a large supply voltage range is required.

US Patent:

43238467, Apr 6, 1982

Filed:

Jun 21, 1979

Appl. No.:

6/050724

Inventors:

Tegze P. Haraszti - Garden Grove CA

Assignee:

Rockwell International Corporation - El Segundo CA

International Classification:

G05F 304

US Classification:

323311

Abstract:

A voltage generator circuit for producing an output voltage which tracks the threshold voltage variation of the MOS devices on the semiconductor body, the magnitude of the output voltage being equal to or slightly greater than the absolute magnitude of the threshold voltages. The circuit includes two MOSFETs having their conduction paths connected in electrical series, each MOSFET having an applied gate-to-source voltage of 2V. sub. T. The voltage output terminal is connected to the node between the series connected conduction path terminals of the first and second MOSFETs. Three series connected MOSFETs which form a source follower circuit are also provided for providing the required gate-to-source voltage on the first two MOSFETs.

US Patent:

41692330, Sep 25, 1979

Filed:

Feb 24, 1978

Appl. No.:

5/880722

Inventors:

Tegze P. Haraszti - Garden Grove CA

Assignee:

Rockwell International Corporation - El Segundo CA

International Classification:

H03K 520
G11C 700

US Classification:

307355

Abstract:

A high performance sense amplifier that is preferably fabricated from complementary metal oxide semiconductor field effect transistors (CMOSFETs) and is especially suited for applications in a radiation hardened environment. The sense amplifier of the present invention is characterized by high sensitivity, high gain, good noise immunity, low power dissipation, fast operation, relatively small geometrical size, and good stabilization for temperature and supply effects while providing self-compensation for non-uniformities of electrical parameters which may occur as the result of MOS device processing or exposure to a nuclear radiation event.

US Patent:

20200285574, Sep 10, 2020

Filed:

Sep 26, 2018

Appl. No.:

16/350112

Inventors:

Tegze P. Haraszti - Newport Beach CA, US

International Classification:

G06F 12/02
G06F 3/06
G11C 16/10
G11C 16/04
H03M 13/37

Abstract:

Method and machine for storing massive amounts of information in very small spaces; and for combining that with the characteristics of very high speed program, write and read operations, small power consumption, great environmental tolerance, radiation hardness and reliability, small size and weight, at low costs, are provided. The method associates, couples and transforms content symbol and address symbol to each other, stores and memorizes the associations, couplings and transforms, by and in a symbol transformer machine. The first augmentation dissects the symbol into symbol parts, operates on and with symbol parts, and combines symbol parts. The second augmentation operates on and with polyadic numbers and polyadic number parts. The third and fourth augmentations comprise conversions and auxiliary storage of symbols and symbol parts, respectively. Embodiments of symbol transformer machine comprise one or a plurality of crosspoint arrays, transistor circuits, memory devices, logic gates, registers, transcoders, and auxiliary memories. In any combination, the invention allows for the use of any and all of the processing steps, augmentations and embodiments.