Terence C Lee

US Patent:

55965873, Jan 21, 1997

Filed:

Mar 29, 1993

Appl. No.:

8/039947

Inventors:

Raymond W. Douglas - Orinda CA
Philip J. Stinger - Otter Shaw, GB2
Harold W. Ng - Concord CA
Terence N. Lee - Oakland CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R 3128

US Classification:

371 27

Abstract:

Method and apparatus for preparing sequences of test vectors to test for proper assembly of complex custom IC's onto printed circuit boards. The method, operating with appropriate apparatus for driving and sensing pins of a sample IC, automatically prepares an in-circuit test vector sequence, starting with only rudimentary information about the pins of the IC and no information at all about the functions or internal structure of the IC. The method makes use of goal-seeking and minimization procedures. The goal-seeking procedure constructs vector sequences from pseudorandom numbers until it finds a sequence which effectively and stably attains a set of pin fault coverage goals stated by the human operator. The minimization procedure then shortens the sequence, discarding excess vectors and keeping only those which efficiently contribute to the attainment of the pin fault coverage goal. The human operator may suggest sets of goals and starting sets of vectors, and may define clock events and data exchange cycles of multiple vectors in order to give the process a head start.