Terry C Coughlin

US Patent:

20020089350, Jul 11, 2002

Filed:

Jan 10, 2001

Appl. No.:

09/758054

Inventors:

Anthony Correale - Raleigh NC, US
Terry Coughlin - Endicott NY, US
Douglas Stout - Milton VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K019/0175

US Classification:

326/083000

Abstract:

The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

US Patent:

20030146774, Aug 7, 2003

Filed:

Feb 7, 2002

Appl. No.:

10/072165

Inventors:

Terry Coughlin - Endicott NY, US
Geoffrey Wang - Endicott NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H03K019/003

US Classification:

326/030000

Abstract:

A method of, and a circuit for, impedance control. The method comprises the steps of providing an input/output cell having a controllable input/output impedance, providing a reference cell including a node having a variable voltage, and comparing the voltage of the node to a reference voltage. The voltage of the node is adjusted during a defined period and according to a defined procedure, and during that defined period, a digital signal is generated. That digital signal is transmitted to the input/output cell to adjust the input/output impedance. Preferably, the circuit is embodied as a digital controller designed as a synthesized core or macro. The advantage of this implementation is that it never has to be redesigned in future technologies. The digital controller may be carried over to future technologies in the form of VHDL code, which is pure logic and independent of technology.

US Patent:

20050127972, Jun 16, 2005

Filed:

Dec 11, 2003

Appl. No.:

10/732950

Inventors:

David Chen - Endwell NY, US
Terry Coughlin - Endicott NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H03K003/12
H01L021/20
H03K003/037
H03K003/356
H03K003/286
H01L029/00

US Classification:

327218000, 257532000

Abstract:

A decoupling capacitor includes a fixed resistance in series with the capacitor, the resistance formed by contacts connecting a polysilicon layer to metal and a diffusion layer to metal; the contacts being of location and quantity sufficient for limiting defect current while allowing the capacitor to function at high frequency. N pairs of contacts in at least two sets of contacts are separated by a distance K sufficient to achieve a leakage limiting resistance of R and a bandwidth limiting resistance of R/

US Patent:

20050160385, Jul 21, 2005

Filed:

Jan 20, 2004

Appl. No.:

10/760502

Inventors:

Terry Coughlin - Endicott NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F017/50

US Classification:

716003000, 716001000

Abstract:

A method, apparatus and computer program product are provided for implementing application specific integrated circuit (ASIC) designs having high performance and reduced leakage current. Standard voltage threshold (SVT) circuits in a SVT circuit library are identified. For each SVT circuit, each SVT PFET is replaced with a low voltage threshold (LVT) PFET to provide a hybrid alternate voltage threshold (AVT) circuit. Then the AVT circuits are saved in an alternate voltage threshold circuit library. The AVT circuit library provides enhanced performance as compared to the SVT circuit library without the high leakage current resulting from a LVT circuit library.

US Patent:

55086454, Apr 16, 1996

Filed:

Mar 28, 1995

Appl. No.:

8/412241

Inventors:

Gregg R. Castellucci - Plattsburgh NY
Terry C. Coughlin - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 522

US Classification:

327 77

Abstract:

A signal detector circuit in a data receiver including a programmable hysteresis circuit for setting and detecting the presence of both a threshold minimum data signal level and a reset signal level higher than the minimum signal level.

US Patent:

6127867, Oct 3, 2000

Filed:

Oct 28, 1998

Appl. No.:

9/181399

Inventors:

Terry Cain Coughlin - Johnson City NY
William Fredrick Lawson - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3289

US Classification:

327202

Abstract:

A latched receiver circuit capable of receiving data and clock simultaneously. New data is latched at every clock cycle without delay or buffering of the data or the clock. The latched receiver may also receive and latch small signals without the aid of a receiver preamp or added delay.

US Patent:

61811939, Jan 30, 2001

Filed:

Oct 8, 1999

Appl. No.:

9/415862

Inventors:

Terry C. Coughlin - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 301

US Classification:

327534

Abstract:

A high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called "dual-gate" or "thick-oxide" process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.

US Patent:

62625993, Jul 17, 2001

Filed:

Apr 6, 2000

Appl. No.:

9/544132

Inventors:

Terry C. Coughlin - Endicott NY
William F. Lawson - Vestal NY
Joseph M. Milewski - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 190175
H03L 500

US Classification:

326 81

Abstract:

A low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the higher voltage logic level signals. A first predrive stage is provided, comprising buffers (e. g. , CMOS inverters) for tuning and balancing the circuit and the core signal combining circuit of a second predrive stage, thereby enabling IC designers to reduce the size of transistors in the level-shifting stage and providing more flexibility in the tuning of the predrive circuitry to synchronize or balance the logical transitions of the complementary transistors of the output driving stage. The invention provides a faster balanced level-shifting output buffer which enables higher frequency operation.