Terry Eugene Downs

US Patent:

7894978, Feb 22, 2011

Filed:

Apr 1, 2008

Appl. No.:

12/060421

Inventors:

James T. Kurnik - Linden MI, US
Terry E Downs - Canton MI, US
Ronald J. Gaynier - Ann Arbor MI, US

International Classification:

G06F 19/00

US Classification:

701115, 702 85

Abstract:

A tamper detection system for a control module of a vehicle comprises first nonvolatile memory that stores N rewriteable components including at least one of calibration and software that is used to operate a controlled device of the vehicle, wherein N is an integer greater than zero. The N rewriteable components include an embedded part number (EPN) and an embedded verification number (EVN). Second nonvolatile memory includes a history buffer. A tampering detection module includes a calculated verification number (CVN) generator that generates a CVN for at least one of the N rewriteable components and that stores the CVN in the history buffer. A locking module selectively locks the history buffer under certain conditions.

US Patent:

60214783, Feb 1, 2000

Filed:

Jun 30, 1997

Appl. No.:

8/885886

Inventors:

Scott Martin Kerstein - Redford MI
William Eugene Gioiosa - Dearborn Heights MI
Terry Eugene Downs - North Wales PA

Assignee:

Ford Motor Company - Dearborn MI

International Classification:

G11C 700
G11C 800
G11C 1140

US Classification:

711167

Abstract:

Burst memory transfer from a memory to a microprocessor (CPU) is accomplished using analysis including determining first and second conditions. If an output enable is consecutively activated for more than one consecutive system clock cycle, following the address phase, the memory will initiate a burst transfer sequence. The addresses of subsequent data bytes or words following the first byte or word are determined by the memory advancing or incrementing its internal address counter until the burst transfer has been suspended or terminated. If the output enable pin is deactivated prior to the next address phase requested by the CPU, burst transfer will be suspended until the output enable pin is activated again. If the CPU requests the next address phase (chip enable activated) from the memory while the output enable is activated, the burst in progress will be terminated.

US Patent:

55028357, Mar 26, 1996

Filed:

Aug 31, 1994

Appl. No.:

8/298885

Inventors:

Chinh H. Le - Austin TX
Gerald E. Vauk - Austin TX
Terry E. Downs - Farmington Hills MI

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1200

US Classification:

395496

Abstract:

An integrated circuit microprocessor (30) reads data from an external memory device (22, 23) through early overlapping memory access cycles, thus allowing efficient accesses to slower-speed memory. The microprocessor (30) drives a first address and activates a chip enable signal during a first clock period. The chip enable signal causes the external memory device to latch the first address and begin a first memory access. During a second, subsequent clock period, the microprocessor (30) provides a second address and again activates the chip enable signal. During a third clock period, subsequent to the second clock period, the microprocessor (30) latches a first data element associated with the first address. This early overlapping memory access type allows a memory device with a slow memory core to pipeline the second access prior to completion of the first access, increasing system efficiency.