Terry D Downs

US Patent:

55028357, Mar 26, 1996

Filed:

Aug 31, 1994

Appl. No.:

8/298885

Inventors:

Chinh H. Le - Austin TX
Gerald E. Vauk - Austin TX
Terry E. Downs - Farmington Hills MI

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1200

US Classification:

395496

Abstract:

An integrated circuit microprocessor (30) reads data from an external memory device (22, 23) through early overlapping memory access cycles, thus allowing efficient accesses to slower-speed memory. The microprocessor (30) drives a first address and activates a chip enable signal during a first clock period. The chip enable signal causes the external memory device to latch the first address and begin a first memory access. During a second, subsequent clock period, the microprocessor (30) provides a second address and again activates the chip enable signal. During a third clock period, subsequent to the second clock period, the microprocessor (30) latches a first data element associated with the first address. This early overlapping memory access type allows a memory device with a slow memory core to pipeline the second access prior to completion of the first access, increasing system efficiency.