Terry A Downs

US Patent:

60214783, Feb 1, 2000

Filed:

Jun 30, 1997

Appl. No.:

8/885886

Inventors:

Scott Martin Kerstein - Redford MI
William Eugene Gioiosa - Dearborn Heights MI
Terry Eugene Downs - North Wales PA

Assignee:

Ford Motor Company - Dearborn MI

International Classification:

G11C 700
G11C 800
G11C 1140

US Classification:

711167

Abstract:

Burst memory transfer from a memory to a microprocessor (CPU) is accomplished using analysis including determining first and second conditions. If an output enable is consecutively activated for more than one consecutive system clock cycle, following the address phase, the memory will initiate a burst transfer sequence. The addresses of subsequent data bytes or words following the first byte or word are determined by the memory advancing or incrementing its internal address counter until the burst transfer has been suspended or terminated. If the output enable pin is deactivated prior to the next address phase requested by the CPU, burst transfer will be suspended until the output enable pin is activated again. If the CPU requests the next address phase (chip enable activated) from the memory while the output enable is activated, the burst in progress will be terminated.