Thang Andy Tran

US Patent:

7230960, Jun 12, 2007

Filed:

Mar 24, 2004

Appl. No.:

10/808732

Inventors:

Hoang Nguyen - Livermore CA, US
Dong Ho Choi - Palo Alto CA, US
Ross D. Pace - San Jose CA, US
Thang Tran - San Jose CA, US
Weizhi Wang - San Jose CA, US
Alan Lim - San Jose CA, US

Assignee:

Bookham Technology PLC - Abingdon

International Classification:

H01S 3/121
H01S 3/10
H01S 3/13
H01S 3/08

US Classification:

372 20, 372 14, 372 29022, 372102

Abstract:

Tunable external cavity lasers are used in applications such as interferometry, FM spectroscopy, and optical communications equipment testing. Mode hop free high bandwidth frequency modulation operation is desired in a tunable external cavity laser. This application describes new and novel techniques for controlling the output wavelength of a tunable external cavity laser while suppressing mode hop.

US Patent:

8414361, Apr 9, 2013

Filed:

Aug 13, 2010

Appl. No.:

12/856521

Inventors:

Phuong Van Nguyen - San Jose CA, US
Thang Van Tran - San Jose CA, US

International Classification:

B24B 7/00

US Classification:

451285, 451286, 451287, 451 28, 451290, 451490

Abstract:

A template for polishing Silicon Carbide, Sapphire, Germanium, Silicon and pattern wafers having a slurry inlet, channels, outlets and pockets for holding said wafers terminating in peripheral vacuum ports in order to facilitate an efficient flow of slurry over the semiconductor wafers during a polishing process.

US Patent:

20210389979, Dec 16, 2021

Filed:

Jun 15, 2020

Appl. No.:

16/901012

Inventors:

- Hsinchu City, TW
Thang Minh Tran - Saratoga CA, US

Assignee:

ANDES TECHNOLOGY CORPORATION - Hsinchu City

International Classification:

G06F 9/48
G06F 9/30
G06F 9/38

Abstract:

A data processing system includes a priority scheduler and execution queue between an instruction decode unit and a functional function. The priority scheduler determines whether a source operand data specified by an instruction issued by the instruction decode unit is ready or not. The priority scheduler prioritizes the decoding instruction having all of the source operand data ready over the ready instruction from the execution queue to send to the functional unit. The decoding instruction having a data dependency is placed into the execution queue.

US Patent:

20210374070, Dec 2, 2021

Filed:

Jun 1, 2020

Appl. No.:

16/888873

Inventors:

- Hsinchu City, TW
Thang Minh Tran - Saratoga CA, US

Assignee:

ANDES TECHNOLOGY CORPORATION - Hsinchu City

International Classification:

G06F 12/1027

Abstract:

A microprocessor includes a translation look-aside buffer (TLB) having a plurality of TLB entries addressable by a branch address and having a branch target buffer (BTB), including a plurality of BTB entries addressable by the branch address. Each TLB entry includes a virtual address. Each BTB entry including a branch tag-way data and a target tag-way data. To perform a branch prediction, the BTB and TLB are accessed, where the TLB way associative data representing one of N sets of TLB entries is used to determine BTB hit or BTB miss. If BTB hit, the branch target address of the branch address may be obtained by accessing the TLB using target tag-way data in the BTB, or by using the branch page address when a same page bit in the hit BTB entry is set.

US Patent:

20210326141, Oct 21, 2021

Filed:

Apr 20, 2020

Appl. No.:

16/853717

Inventors:

- Hsinchu CIty, TW
Thang Minh Tran - Saratoga CA, US

Assignee:

ANDES TECHNOLOGY CORPORATION - Hsinchu City

International Classification:

G06F 9/38
G06F 9/22
G06F 9/30

Abstract:

In the disclosure, the microprocessor resolves the conflicts in decode stage and schedules the instruction to be executed at a future time. The instruction is issued to an execution queue until the scheduled time in the future when it is dispatched to a functional unit for execution. The disclosure uses a counter for the functional unit to track when the resource is available in the future to accept the next instruction. The disclosure also tracks the future N cycles when the register file read and write ports are scheduled to read and write operand data.

US Patent:

20210311741, Oct 7, 2021

Filed:

Apr 7, 2020

Appl. No.:

16/842684

Inventors:

- Hsinchu City, TW
Thang Minh Tran - Saratoga CA, US

Assignee:

ANDES TECHNOLOGY CORPORATION - Hsinchu City

International Classification:

G06F 9/30
G06F 1/08
G06F 1/12

Abstract:

A processor that includes a register file, a read shifter, a decode unit and a plurality of functional units is introduced. The register file includes a read port. The read shifter includes a plurality of shifter entries and is configured to shift out a shifter entry among the plurality of shifter entries every clock cycle. Each of the plurality of shifter entries is associated with a clock cycle and each of the plurality of shifter entries comprises a read value that indicates an availability of the read port of the register file for a read operation in the clock cycle. The decode unit is coupled to the read shifter and is configured to decode and issue an instruction based on the read values included in the plurality of shifter entries of the read shifter. The plurality of functional units is coupled to the decode unit and the register file and is configured to execute the instruction issued by the decode unit and perform the read operation to the read port of the register file.

US Patent:

20210311743, Oct 7, 2021

Filed:

Apr 1, 2020

Appl. No.:

16/836931

Inventors:

- Hsinchu City, TW
Thang Minh Tran - Saratoga CA, US

Assignee:

ANDES TECHNOLOGY CORPORATION - Hsinchu City

International Classification:

G06F 9/38
G06F 1/10

Abstract:

A microprocessor using a counter in a scoreboard is introduced to handle data dependency. The microprocessor includes a register file having a plurality of registers mapped to entries of the scoreboard. Each entry of the scoreboard has a counter that tracks the data dependency of each of the registers. The counter decrements for every clock cycle until the counter resets itself when it counts down to 0. With the implementation of the counter in the scoreboard, the instruction pipeline may be managed according to the number of clock cycles of a previous issued instruction takes to access the register which is recorded in the counter of the scoreboard.

US Patent:

20210303305, Sep 30, 2021

Filed:

Mar 31, 2020

Appl. No.:

16/836864

Inventors:

- Hsinchu City, TW
Thang Minh Tran - Saratoga CA, US

Assignee:

ANDES TECHNOLOGY CORPORATION - Hsinchu City

International Classification:

G06F 9/30

Abstract:

A processor that includes a register file, a latency shifter, a decode unit and a plurality of functional units is introduced. The register file includes a write port. The latency shifter includes a plurality of shifter entries and shifts out a shifter entry among the shifter entries every clock cycle. Each of the shifter entries is associated with a clock cycle and each of shifter entries includes a writeback value that indicates whether the write port of the register file is available for a writeback operation in the associated clock cycles. The decode unit is configured to decode an instruction and issue the instruction according to the writeback value of the latency shifter. The functional units are coupled to the decode unit and the register file and are configured to execute the instruction issued by the decode unit and perform writeback operation to the write port of the register file.

Address:

538 Downsglen Way, San Jose, CA 95133

Phone:

(408)5732463

VIN:

5TDYK3DC1BS126838

Make:

TOYOTA

Model:

SIENNA

Year:

2011

Address:

1735 Ramstree Dr, San Jose, CA 95131

Phone:

(408)3479833

VIN:

4T1BE46K97U178045

Make:

TOYOTA

Model:

CAMRY

Year:

2007