Thang Trong Tran

US Patent:

20220382547, Dec 1, 2022

Filed:

May 25, 2021

Appl. No.:

17/329181

Inventors:

- Hsinchu City, TW
Thang Minh Tran - Tustin CA, US

Assignee:

ANDES TECHNOLOGY CORPORATION - Hsinchu City

International Classification:

G06F 9/30
G06F 9/38
G06F 13/16

Abstract:

A microprocessor and a method for issuing a load/store instruction is introduced. The microprocessor includes a decode/issue unit, a load/store queue, a scoreboard, and a load/store unit. The scoreboard includes a plurality of scoreboard entries, in which each scoreboard entry includes an unknown bit value and a count value, wherein the unknown bit value or the count value is set when the instructions are issued. The decode/issue unit checks for WAR, WAW, and RAW data dependencies from the scoreboard, dispatches the load/store instructions to the load/store queue with the recorded scoreboard values. The load/store queue is configured to resolve the data dependencies and dispatches the load/store instructions to the load/store unit for execution.