Thomas E Cynkar

US Patent:

7280002, Oct 9, 2007

Filed:

Mar 3, 2005

Appl. No.:

11/070985

Inventors:

Alvin Leng Sun Loke - Fort Collins CO, US
Tin Tin Wee - Fort Collins CO, US
Robert Keith Barnes - Fort Collins CO, US
Kari Lee Arave - Fort Collins CO, US
Thomas Edward Cynkar - Fort Collins CO, US
James Ruhl Pfiester - Fort Collins CO, US

Assignee:

Avago Technologies General IP Pte Ltd - Singapore

International Classification:

H03B 5/12

US Classification:

331177V, 331 36 C

Abstract:

A method and apparatus is presented for generating a reference voltage that biases a metal-oxide-semiconductor (MOS) transistor used as a varactor in capacitive tuning applications. In one embodiment, a biasing circuit is implemented. The biasing circuit comprises a diode-clamped FET and an element coupled to the diode-clamped FET at a connection point. The element produces a constant current through the diode-clamped FET. A voltage is produced at the connection point. The voltage is one gate overdrive plus a threshold voltage above ground or one gate overdrive plus a threshold voltage below VDD. Establishing a threshold voltage in this way enables the biasing circuit to track an ideal voltage of a varactor that is coupled to the biasing circuit through the threshold voltage.

US Patent:

7952398, May 31, 2011

Filed:

Apr 27, 2007

Appl. No.:

11/741115

Inventors:

Manuel Salcido - Fort Collins CO, US
J. Ken Patterson - Fort Collins CO, US
Thomas Edward Cynkar - Fort Collins CO, US

Assignee:

Avago Technologies Enterprise IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H03B 1/00

US Classification:

327109, 327534

Abstract:

A receiver suitable for applications that desire a common-mode voltage range from approximately 0. 7V to approximately 0. 9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the receiver assembly. A bias signal directs the bridge circuit over a set of worst case conditions.

US Patent:

20150028470, Jan 29, 2015

Filed:

Jul 23, 2013

Appl. No.:

13/948196

Inventors:

- Singapore, SG
Thomas E. Cynkar - Fort Collins CO, US

Assignee:

Avago Technologies General IP (Singapore) Pte.Ltd. - Singapore

International Classification:

H01L 23/498

US Classification:

257737, 438121

Abstract:

A silicon interconnect structure includes a peripheral outer via in a silicon substrate, a solid core inner via in the silicon substrate, the solid core inner via coaxial with the peripheral outer via to form a coaxial via structure, a metal interconnect stack formed over a first surface of the peripheral outer via and the solid core inner via, at least portions of the metal interconnect stack forming an electrical connection with the peripheral outer via and the solid core inner via, first contact pads on a surface of the metal interconnect stack, and second contact pads on an exposed surface of the peripheral outer via and the solid core inner via.