Thomas J Harrington

US Patent:

49435370, Jul 24, 1990

Filed:

Jun 27, 1989

Appl. No.:

7/372077

Inventors:

Thomas E. Harrington - Carrollton TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

H01L 21265
H01L 2700

US Classification:

437 34

Abstract:

A CMOS integrated circuit, in which the PMOS devices each include a buried channel region (26). The P+ source/drain regions (54) and (56) are separated from the channel region (26) by N-type lateral field isolating regions (58) and (60). Whenever a voltage negative enough to turn on the channel is applied, the isolating regions will be inverted by the electric fields from the corners of the gate. Thus, the value of the transistor's threshold voltage is not changed. However, these lateral field isolating regions provide an electric field modification which helps to minimize drain-induced barrier lowering, and thereby reduces the leakage current of the device in the off state. Preferably the lateral field isolating regions are formed by a doping which is maximal at the same depth (below the gate oxide) at which the threshold-voltage-adjust doping of the channel is maximal. The preferred CMOS process provides lateral field isolating regions on the PMOS devices, and also provides LDD regions on the NMOS devices. The lateral field isolating regions in the PMOS transistors are formed by a blanket N-type implant, and the LDD regions in the NMOS transistors are formed by a patterned implant.

US Patent:

51594269, Oct 27, 1992

Filed:

Dec 20, 1990

Appl. No.:

7/632223

Inventors:

Thomas E. Harrington - Carrollton TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

H01L 2702

US Classification:

357 42

Abstract:

A battery-backed integrated circuit, which receives battery power to maintain data (or logic states) when the system (external) power supply goes down. The battery power input is connected through a diode, so that the battery cannot be charged when the system power supply is active. The battery isolation diode is a junction diode, which is surrounded by a second junction. The battery junction collects minority carriers which will be generated when the battery protection diode is forward biased (i. e. when the integrated circuit is being powered from the battery). Otherwise, minority carriers can diffuse to other junctions, to cause leakage currents which can significantly degrade the lifetime of a low-powered device.

US Patent:

56820518, Oct 28, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/480725

Inventors:

Thomas E. Harrington - Carrollton TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

H01L 2976

US Classification:

257369

Abstract:

A CMOS integrated circuit, in which the PMOS devices each include a buried channel region (26). The P+ source/drain regions (54) and (56) are separated from the channel region (26) by N-type lateral field isolating regions (58) and (60). Whenever a voltage negative enough to turn on the channel is applied, the isolating regions will be inverted by the electric fields from the comers of the gate. Thus, the value of the transistor's threshold voltage is not changed. However, these lateral field isolating regions provide an electric field modification which helps to minimize drain-induced barrier lowering, and thereby reduces the leakage current of the device in the off state. Preferably the lateral field isolating regions are formed by a doping which is maximal at the same depth (below the gate oxide) at which the threshold-voltage-adjust doping of the channel is maximal. The preferred CMOS process provides lateral field isolating regions on the PMOS devices, and also provides LDD regions on the NMOS devices. The lateral field isolating regions in the PMOS transistors are formed by a blanket N-type implant, and the LDD regions in the NMOS transistors are formed by a patterned implant.

US Patent:

56887221, Nov 18, 1997

Filed:

Jun 16, 1992

Appl. No.:

7/899409

Inventors:

Thomas E. Harrington - Carrollton TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

H01L 21336
H01L 218238

US Classification:

438217

Abstract:

A CMOS integrated circuit, in which the PMOS devices each include a buried channel region (26). The P+ source/drain regions (54) and (56) are separated from the channel region (26) by N-type lateral field isolating regions (58) and (60). Whenever a voltage negative enough to turn on the channel is applied, the isolating regions will be inverted by the electric fields from the comers of the gate. Thus, the value of the transistor's threshold voltage is not changed. However, these lateral field isolating regions provide an electric field modification which helps to minimize drain-induced barrier lowering, and thereby reduces the leakage current of the device in the off state. Preferably the lateral field isolating regions are formed by a doping which is maximal at the same depth (below the gate oxide) at which the threshold-voltage-adjust doping of the channel is maximal. The preferred CMOS process provides lateral field isolating regions on the PMOS devices, and also provides LDD regions on the NMOS devices. The lateral field isolating regions in the PMOS transistors are formed by a blanket N-type implant, and the LDD regions in the NMOS transistors are formed by a patterned implant.

US Patent:

48623105, Aug 29, 1989

Filed:

Apr 29, 1988

Appl. No.:

7/187864

Inventors:

Thomas E. Harrington - Carrollton TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

H02J 902

US Classification:

361 58

Abstract:

A battery protection device for preventing battery charging comprises a diode formed with a p+ region (36) within an N-type region (34). The diode is completely surrounded by a P-well (32) to prevent minority carrier injection from the N-type region (34) to the N-type substrate (30). The N-type region (34) is connected to the P-well (32) and to the substrate (30) through an electrical connection (43). By preventing minority carrier injection into the substrate (30), leakage through a parasitic transistor is prevented.

US Patent:

49065882, Mar 6, 1990

Filed:

Jun 23, 1988

Appl. No.:

7/210242

Inventors:

Thomas E. Harrington - Carrollton TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

H01L 21265
H01L 2700

US Classification:

437 44

Abstract:

An enclosed buried channel device includes a buried channel region (26) disposed under a gate electrode (24). Source and drain regions (54) and (56) are formed on either side of gate electrode (26). The source/drain regions (54) and (56) are separated from the various channel region (26) by isolating regions of N-type material (58) and (60), respectively. The isolating regions (58) and (60) are operable to be inverted during normal operation of the transistor when the transistor is conducting, but are operable to isolate fields on the drain side of the transistor from the buried channel region (26) to lower the leakage current of the device in the off state.

US Patent:

51810913, Jan 19, 1993

Filed:

Sep 16, 1991

Appl. No.:

7/760411

Inventors:

Thomas E. Harrington - Carrollton TX
Robert D. Lee - Denton TX

Assignee:

Dallas Semiconductor Corp. - Dallas TX

International Classification:

H01L 2978

US Classification:

257355

Abstract:

A battery-backed integrated circuit, with a double diode structure connected to signal lines. In the double diode structure, a first junction is three-dimensionally enclosed by a second junction, so that minority carriers generated at the first junction will be collected at the second junction. Thus, when a negative transient voltage appears on the signal line, the first junction can be forward biassed to source the needed current from ground, with minimal minority carrier injection.

US Patent:

49807463, Dec 25, 1990

Filed:

Apr 28, 1989

Appl. No.:

7/344734

Inventors:

Thomas E. Harrington - Carrollton TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

H01L 2702

US Classification:

357 42

Abstract:

A battery-backed integrated circuit, which receives battery power to maintain data (or logic states) when the system (external) power supply goes down. The battery power input is connected through a diode, so that the battery cannot be charged when the system power supply is active. The battery isolation diode is a junction diode, which is surrounded by a second junction. The second junction collects minority carriers which will be generated when the battery protection diode is forward biased (i. e. when the integrated circuit is being powered from the battery). Otherwise, minority carriers can diffuse to other junctions, to cause leakage currents which can significantly degrade the lifetime of a low-powered device.