Thomas J Herman

US Patent:

6346726, Feb 12, 2002

Filed:

Nov 8, 1999

Appl. No.:

09/436302

Inventors:

Thomas Herman - Manhattan Beach CA

Assignee:

International Rectifier Corp. - El Segundo CA

International Classification:

H01L 2976

US Classification:

257327, 257328, 257365, 257408, 257343

Abstract:

A power MOSFET die with a minimized figure of merit has of a planar stripe MOSFET geometry in which parallel diffused bases (or channels) are formed by implantation and diffusion of impurities through parallel elongated and spaced polysilicon stripes wherein the polysilicon line width is from about 3. 2 to 3. 4 microns, preferably 3. 4 microns; the polyline spacing is from about 1 to 4 microns, preferably 1. 5 microns and the diffused bases are spaced by greater than about 0. 8 microns. The polysilicon stripes act as masks to the sequential formation of first base stripes, the source stripes and second higher concentration base stripes which are deeper than the first base stripes. Insulation side wall spacers are used to define a contact etch for the source contact. The above design geometry is used for both the forward control MOSFET and the synchronous rectifier MOSFET of a buck converter circuit.

US Patent:

6781203, Aug 24, 2004

Filed:

Nov 9, 2001

Appl. No.:

10/044427

Inventors:

Thomas Herman - Manhattan Beach CA
Harold Davis - San Diego CA
Kyle Spring - Temecula CA
Jianjun Cao - Temecula CA

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L 2946

US Classification:

257341, 257329, 257330, 257331

Abstract:

A vertical conduction MOSFET having a reduced on resistance R as well as reduced threshold voltage V , and an improved resistance to punchthrough and walkout has an extremely shallow source diffusion, of less than 0. 3 microns in depth and an extremely shallow channel diffusion, of less than about 3 microns in depth. In a P channel version, phosphorus is implanted into the bottom of a contact trench and into the channel region with an implant energy of 400 keV for a singly charged phosphorus ion or 200 keV for a doubly charged ion, thereby to prevent walkout of the threshold voltage.

US Patent:

6955970, Oct 18, 2005

Filed:

Nov 28, 2000

Appl. No.:

09/723655

Inventors:

Thomas Herman - Manhattan Beach CA, US

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L021/336

US Classification:

438306, 290301, 290527

Abstract:

A power MOSFET die with a minimized figure of merit has of a planar stripe MOSFET geometry in which parallel diffused bases (or channels) are formed by implantation and diffusion of impurities through parallel elongated and spaced polysilicon stripes wherein the polysilicon line width is from about 3. 2 to 3. 4 microns, preferably 3. 4 microns; the polyline spacing is from about 1 to 4 microns, preferably 1. 5 microns and the diffused bases are spaced by greater than about 0. 8 microns. The polysilicon stripes act as masks to the sequential formation of first base stripes, the source stripes and second higher concentration base stripes which are deeper than the first base stripes. Insulation side wall spacers are used to define a contact etch for the source contact. The above design geometry is used for both the forward control MOSFET and the synchronous rectifier MOSFET of a buck converter circuit.

US Patent:

7180152, Feb 20, 2007

Filed:

Jul 8, 2004

Appl. No.:

10/888690

Inventors:

Thomas Herman - Manhattan Beach CA, US

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L 23/58

US Classification:

257492, 257491, 257496, 257E21531, 257E21537

Abstract:

A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0. 1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the arsenic is not intentionally driven. Device junction are then diffused into the epitaxially grown layer.

US Patent:

7408208, Aug 5, 2008

Filed:

Mar 19, 2007

Appl. No.:

11/725430

Inventors:

Thomas Herman - Manhattan Beach CA, US

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L 31/0328

US Classification:

257194, 257192, 257E29248, 257E29246

Abstract:

A III-nitride power semiconductor device that includes a two dimensional electron gas having a low field region under the gate thereof.

US Patent:

7482205, Jan 27, 2009

Filed:

Dec 11, 2006

Appl. No.:

11/636763

Inventors:

Thomas Herman - Manhattan Beach CA, US

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L 21/332
H01L 21/336

US Classification:

438138, 438133, 438135, 438459, 257339, 257492, 257493, 257E21335, 257E21383

Abstract:

A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0. 1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the arsenic is not intentionally driven. Device junction are then diffused into the epitaxially grown layer.

US Patent:

7719030, May 18, 2010

Filed:

Mar 28, 2007

Appl. No.:

11/692437

Inventors:

Thomas Herman - Manhattan Beach CA, US

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L 29/739
H01L 31/00

US Classification:

257194, 257E29144, 257E29253

Abstract:

A low contact resistance ohmic contact for a III-Nitride or compound semiconductor wafer or die consists of 4 layers of Ti, AlSi, Ti and TiW. The AlSi has about 1% Si. The layers are sequentially deposited as by sputtering, are patterned and plasma etched and then annealed in a rapid thermal anneal process. The use of AlSi in place of pure Al reduces contact resistance by about 15% to 30%.

US Patent:

8264003, Sep 11, 2012

Filed:

Mar 20, 2007

Appl. No.:

11/688338

Inventors:

Thomas Herman - Manhattan Beach CA, US

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L 29/66

US Classification:

257194, 257E29246

Abstract:

A merged gate transistor in accordance with an embodiment of the present invention includes a semiconductor element, a supply electrode electrically connected to a top surface of the semiconductor element, drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the supply electrode, a first gate positioned between the supply electrode and the drain electrode and capacitively coupled to the semiconductor element to form a first portion of the transistor and a second gate positioned adjacent to the first gate, and between the supply electrode and the drain electrode to form a second portion of the transistor, wherein the second gate is also capacitively coupled to the semiconductor element. The first gate is connected to an input voltage signal such that conduction of the first portion is based on a value of the input voltage signal and the second gate is connected to a predetermined constant voltage such that the second portion of the transistor conducts until a voltage difference between the predetermined constant voltage and a voltage at the source electrode reaches a predetermined level.