Thomas J Joyce

US Patent:

50518941, Sep 24, 1991

Filed:

Jan 5, 1989

Appl. No.:

7/294528

Inventors:

Forrest M. Phillips - North Chelmsford MA
Thomas F. Joyce - Westford MA
Ming T. Miu - Chelmsford MA

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 926
G06F 1204

US Classification:

364200

Abstract:

In a data processing system in which the execution unit is implemented to process aligned double word operands, apparatus and an associated method provide for the alingment of a double word operand that is stored across a double work boundary. The two double words each storing a word of the unaligned double word operand are identified and the attributes are compared with the ring number of the associated program. When the comparisons indicate that the two words of the non-aligned double word operand are available to the program, the two double word operands containing the non-aligned words of the double word operand, and the two non-aligned words are stored in a register in an aligned orientation for processing by the execution unit.

US Patent:

46959432, Sep 22, 1987

Filed:

Sep 27, 1984

Appl. No.:

6/655473

Inventors:

James W. Keeley - Hudson NH
Thomas F. Joyce - Westford MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1300
G11C 700

US Classification:

364200

Abstract:

A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.

US Patent:

51485303, Sep 15, 1992

Filed:

Sep 6, 1989

Appl. No.:

7/403554

Inventors:

Thomas F. Joyce - Westford MA
Richard P. Kelly - Nashua NH

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 900
G06F 932

US Classification:

395375

Abstract:

In a data processing system using a virtual memory adressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value.

US Patent:

46413057, Feb 3, 1987

Filed:

Oct 19, 1984

Appl. No.:

6/663101

Inventors:

Thomas F. Joyce - Westford MA
Richard P. Kelly - Nashua NH

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1110
G06F 1114

US Classification:

371 12

Abstract:

A method and apparatus for a microinstruction controlled unit to recover from a read error in reading microinstructions from a control store. The method provides for the overlapping of the execution of a current microinstruction while the next microinstruction is being addressed and read from the control store. Execution of the current microinstruction is begun before it is known whether or not it was read without error. The apparatus provides for aborting the execution of the current microinstruction with the read error and the next microinstruction. During the aborted execution of the next microinstruction, the current microinstruction is reread from the control store and then executed while the next microinstruction is being reread. The execution of microinstructions is aborted in a manner that does not alter the state of the microinstruction controlled unit beyond the point that would inhibit the re-execution of the aborted microinstructions.

US Patent:

52875229, Feb 15, 1994

Filed:

Jun 29, 1990

Appl. No.:

7/546347

Inventors:

Richard P. Brown - Acton MA
Thomas F. Joyce - Westford MA
Steven S. Smith - Nashua NH

Assignee:

Bull HN Information Systems, Inc. - Billerica MA

International Classification:

G06F 1314
G06F 900

US Classification:

395725

Abstract:

A system includes first and second processing units which are interconnected by a bidirectional bus. The first processing unit is a microprocessor chip programmed for executing procedures stored in an on-chip instruction cache unit. The second processing unit receives requests from an external source such as a system bus. The microprocessor chip includes a branch vector facility which connects to the bus. The second processing unit in response to an external request, generates a vector branch address. The processing unit transfers the vector branch address to the branch vector facility for storage along with setting a write indicator. The microprocessor chip, upon detecting that the write indicator was set, branches to the procedure specified by the branch vector address for executing the instructions of the procedure to carry out those operations required for processing the external request or event.

US Patent:

46708359, Jun 2, 1987

Filed:

Oct 19, 1984

Appl. No.:

6/663096

Inventors:

Richard P. Kelly - Nashua NH
Thomas F. Joyce - Westford MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 930

US Classification:

364200

Abstract:

Apparatus that provides interrupt operation in a central processor based system wherein internal subsystems are operated via addresses generated by a next address generator in the processor and sent to control stores associated with each subsystem to thereby read out firmware instructions which are used by a controller in each subsystem to control the operations of same. When a special condition is detected in ones of the subsystems a trap signal is sent to the next address generator which responds by generating a microinstruction address to the subsystem that generated the trap signal. The subsystem responds to the microinstruction to read out a register, the contents of which indicate the status of processing in the subsystem including the special condition. The register contents are forwarded to the processor which tests same to determine the nature of the special condition and calls a microprogram the microinstructions of which are applied to the control store of the subsystem that generated the trap signal. The subsystem responds to the microinstructions to clear the special condition.

US Patent:

47853980, Nov 15, 1988

Filed:

Dec 19, 1985

Appl. No.:

6/811044

Inventors:

Thomas F. Joyce - Westford MA
Ming T. Miu - Chelmsford MA
Forrest M. Phillips - North Chelmsford MA

Assignee:

Honeywell Bull Inc. - Waltham MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.

US Patent:

52838706, Feb 1, 1994

Filed:

Oct 4, 1991

Appl. No.:

7/771296

Inventors:

Thomas F. Joyce - Westford MA
James W. Keeley - Nashua NH

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 1314

US Classification:

395200

Abstract:

A multiprocessor system includes a number of system processors which tightly couple to a system bus to share a main or system memory and a number of on-board memory processors which also are tightly coupled to the system bus. Each processor has a high performance microprocessor which tightly couples to an on-board or local memory through the microprocessor's local bus. System memory is accessible using a memory lock protocol while the local memory is accessible through a bus lock protocol. Each on-board memory processor includes a lock mechanism which enables the processing of memory lock commands directed to its local memory received via the system bus from any other processor and for issuing memory lock commands to system memory.