Thomas E Joyce

US Patent:

50518941, Sep 24, 1991

Filed:

Jan 5, 1989

Appl. No.:

7/294528

Inventors:

Forrest M. Phillips - North Chelmsford MA
Thomas F. Joyce - Westford MA
Ming T. Miu - Chelmsford MA

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 926
G06F 1204

US Classification:

364200

Abstract:

In a data processing system in which the execution unit is implemented to process aligned double word operands, apparatus and an associated method provide for the alingment of a double word operand that is stored across a double work boundary. The two double words each storing a word of the unaligned double word operand are identified and the attributes are compared with the ring number of the associated program. When the comparisons indicate that the two words of the non-aligned double word operand are available to the program, the two double word operands containing the non-aligned words of the double word operand, and the two non-aligned words are stored in a register in an aligned orientation for processing by the execution unit.

US Patent:

46959432, Sep 22, 1987

Filed:

Sep 27, 1984

Appl. No.:

6/655473

Inventors:

James W. Keeley - Hudson NH
Thomas F. Joyce - Westford MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1300
G11C 700

US Classification:

364200

Abstract:

A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.

US Patent:

51485303, Sep 15, 1992

Filed:

Sep 6, 1989

Appl. No.:

7/403554

Inventors:

Thomas F. Joyce - Westford MA
Richard P. Kelly - Nashua NH

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 900
G06F 932

US Classification:

395375

Abstract:

In a data processing system using a virtual memory adressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value.

US Patent:

41077741, Aug 15, 1978

Filed:

Oct 4, 1976

Appl. No.:

5/729065

Inventors:

Thomas F. Joyce - Burlington MA
Michel M. Raguin - Medford MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 916

US Classification:

364200

Abstract:

A method and an apparatus for improving the speed of executing instructions and reducing the microprogram memory requirements in a conventional digital computer system. The method or apparatus incorporates the use of a predetermined bit position in the microinstruction word which is set to a binary one when the microword is the last microword of an executing microprogram. The apparatus is responsive to the electronic representation of the binary one signal to cause the microinstruction execution sequence to branch to a predetermined location in the microprogram memory for execution of the following microinstruction; thus, eliminating at least one step in returning to a common address for starting the execution of another microprogram.

US Patent:

42143039, Jul 22, 1980

Filed:

Dec 22, 1977

Appl. No.:

5/863093

Inventors:

Thomas F. Joyce - Burlington MA
Thomas O. Holtey - Newton Lower Falls MA
William Panepinto - Tewksbury MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A word oriented data processing system includes a plurality of system units all connected in common to a system bus. Included are a central processor unit (CPU), a memory system and a high speed buffer or cache system. The cache system is also coupled to the CPU. The cache includes an address directory and a data store with each address location of directory addressing its respective word in data store. The CPU requests a word of cache by sending a memory request to cache which includes a memory address location. If the requested word is stored in the data store, then it is sent to the CPU. If the word is not stored in cache, the cache requests the word of memory. When the cache receives the word from memory, the word is sent to the CPU and also stored in the data store.

US Patent:

43085890, Dec 29, 1981

Filed:

Nov 8, 1979

Appl. No.:

6/093096

Inventors:

Thomas F. Joyce - Burlington MA
Richard A. LeMay - Carlisle MA
William E. Woods - Natick MA
Richard P. Brown - Acton MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 750

US Classification:

364748

Abstract:

The performance of a scientific ADD instruction is improved by storing the mantissas of both operands in each of two random access memories, selecting the mantissa with the smaller exponent, shifting that mantissa and performing the ADD operation of adding the mantissas in one machine cycle.

US Patent:

41953410, Mar 25, 1980

Filed:

Dec 22, 1977

Appl. No.:

5/863094

Inventors:

Thomas F. Joyce - Burlington MA
William Panepinto - Tewksbury MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1300
G11C 906

US Classification:

364200

Abstract:

A data processing system includes a central processor subsystem, a main memory subsystem and a cache subsystem, all coupled in common to a system bus. During the overall system initialization process, apparatus in the cache subsystem effects the transfer of information from the main memory subsystem to the cache subsystem to load all address locations of the cache subsystem. The transfer of information from the main memory subsystem to the cache subsystem starts from the lowest order address locations in main memory and continues from successive address locations until the cache subsystem is fully loaded. This assures that the cache subsystem contains valid information during normal data processing.

US Patent:

46413057, Feb 3, 1987

Filed:

Oct 19, 1984

Appl. No.:

6/663101

Inventors:

Thomas F. Joyce - Westford MA
Richard P. Kelly - Nashua NH

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1110
G06F 1114

US Classification:

371 12

Abstract:

A method and apparatus for a microinstruction controlled unit to recover from a read error in reading microinstructions from a control store. The method provides for the overlapping of the execution of a current microinstruction while the next microinstruction is being addressed and read from the control store. Execution of the current microinstruction is begun before it is known whether or not it was read without error. The apparatus provides for aborting the execution of the current microinstruction with the read error and the next microinstruction. During the aborted execution of the next microinstruction, the current microinstruction is reread from the control store and then executed while the next microinstruction is being reread. The execution of microinstructions is aborted in a manner that does not alter the state of the microinstruction controlled unit beyond the point that would inhibit the re-execution of the aborted microinstructions.