Thomas O Spencer

US Patent:

7509602, Mar 24, 2009

Filed:

Jan 25, 2006

Appl. No.:

11/307130

Inventors:

Subbu Ganesan - Saratoga CA, US
Leonid Alexander Broukhis - Fremont CA, US
Ramesh Narayanaswamy - Palo Alto CA, US
Ian Michael Nixon - Sunnyvale CA, US
Thomas Hanni Spencer - Sunnyvale CA, US

Assignee:

Eve S.A. - Parc Gutenberg, Palaiseau

International Classification:

G06F 17/50
G06F 15/80
G06F 7/38

US Classification:

716 4, 712 22, 712223

Abstract:

A logic simulation acceleration processor optimized for multi-value logic level simulation of electronic systems described in hardware description languages.

US Patent:

7548842, Jun 16, 2009

Filed:

Jan 26, 2006

Appl. No.:

11/307198

Inventors:

Subbu Ganesan - Saratoga CA, US
Leonid Alexander Broukhis - Fremont CA, US
Ramesh Narayanaswamy - Palo Alto CA, US
Ian Michael Nixon - Sunnyvale CA, US
Thomas Hanni Spencer - Sunnyvale CA, US

Assignee:

Eve S.A. - Parc Gutenberg, Palaiseau

International Classification:

G06F 17/50

US Classification:

703 14, 703 13, 703 23, 714 30, 717134, 370258

Abstract:

A scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.

US Patent:

8359186, Jan 22, 2013

Filed:

Jun 20, 2007

Appl. No.:

11/766017

Inventors:

Subbu Ganesan - Saratoga CA, US
Ramesh Narayanaswamy - Palo Alto CA, US
Ian Michael Nixon - Sunnyvale CA, US
Leonid Alexander Broukhis - Fremont CA, US
Thomas Hanni Spencer - Sunnyvale CA, US

International Classification:

G06F 17/50

US Classification:

703 14, 703 13, 703 23, 71 30, 717134, 370258

Abstract:

An RTL hardware description language simulation accelerator and circuit emulator which operates on data driven asynchronous completion handshaking principles. Deploying Muller C elements to control latches, the system does not depend on externally provided clocks or internal timing circuits with delay logic or clock generators. Each levelized domain of logic signals a successor level to begin execution of instructions with a level complete message produced when all its input operands have produced a completion message. Each predecessor stage holds back data production until the successor stage is ready. Each levelized data-driven asynchronous domain evaluation processor is self-timed receiving completion messages from its predecessors, and sending completion messages to its successors.

US Patent:

20060277020, Dec 7, 2006

Filed:

Jan 26, 2006

Appl. No.:

11/307206

Inventors:

Subbu Ganesan - Saratoga CA, US
Leonid Broukhis - Fremont CA, US
Ramesh Narayanaswamy - Palo Alto CA, US
Ian Nixon - Sunnyvale CA, US
Thomas Spencer - Sunnyvale CA, US

Assignee:

THARAS SYSTEMS - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

703014000, 703016000, 703026000

Abstract:

A reconfigurable scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected by reconfigurable high-speed serial links to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.

US Patent:

20060277428, Dec 7, 2006

Filed:

Apr 17, 2006

Appl. No.:

11/379046

Inventors:

SUBBU GANESAN - SARATOGA CA, US
LEONID BROUKHIS - FREMONT CA, US
RAMESH NARAYANASWAMY - PALO ALTO CA, US
IAN NIXON - SUNNYVALE CA, US
THOMAS SPENCER - SUNNYVALE CA, US

Assignee:

Tharas Systems Inc. - Santa Clara CA

International Classification:

G06F 1/00

US Classification:

713500000

Abstract:

A method for generating clocks and delaying execution of an instruction within a hardware accelerator.

US Patent:

20070044079, Feb 22, 2007

Filed:

Jun 30, 2006

Appl. No.:

11/427945

Inventors:

SUBBU GANESAN - SARATOGA CA, US
LEONID BROUKHIS - FREMONT CA, US
RAMESH NARAYANASWAMY - PALO ALTO CA, US
IAN NIXON - SUNNYVALE CA, US
THOMAS SPENCER - SUNNYVALE CA, US

Assignee:

THARAS SYSTEMS INC. - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717136000

Abstract:

A method for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for processors which are scalably interconnected to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors and scheduled and assigned instructions to the processors in an optimal manner.

US Patent:

20090252061, Oct 8, 2009

Filed:

Apr 8, 2008

Appl. No.:

12/099553

Inventors:

David Small - Dublin CA, US
Thomas Spencer - Morganville NJ, US
Canhui Ou - Berkeley CA, US

International Classification:

H04L 12/28

US Classification:

370255

Abstract:

Methods and apparatus to implement a partial mesh virtual private local area network service are disclosed. An example method to implement a partial mesh virtual private local area network service (VPLS) network disclosed herein comprises identifying a desired partial mesh topology of connections for interconnecting a plurality of provider edge devices comprising the VPLS network, and decomposing the partial mesh topology into a plurality of cliques, wherein each clique comprises a respective full mesh topology of connections for interconnecting a respective subset of the plurality of provider edge devices, and wherein a union of the plurality of cliques implements the desired partial mesh topology.