Thomas L Trebelhorn

US Patent:

41612760, Jul 17, 1979

Filed:

Mar 1, 1978

Appl. No.:

5/882518

Inventors:

Eric Sacher - Phoenix AZ
Thomas E. Trebelhorn - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1100

US Classification:

235302

Abstract:

The present invention relates to apparatus and method for testing logic circuit boards for complex logical faults contained therein. A known good identical logic circuit is stimulated by a preselected sequence of binary test patterns and the number of transitions in logical state before achieving a final logical state as well as the final logical state for a number of points within the circuit are monitored and saved. The logic circuit being tested is then stimulated by the same test pattern sequence and the number of transitions and final logical states achieved are compared. Failure to have identity between the known good logical circuit and the logical circuit being tested both as to number of transitions and final logical state achieved for the tested points indicates a malfunction within the board which would not be detected by mere sampling of the final output state alone.

US Patent:

41767802, Dec 4, 1979

Filed:

Dec 6, 1977

Appl. No.:

5/857950

Inventors:

Eric Sacher - Phoenix AZ
Thomas E. Trebelhorn - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1104
G01R 1512

US Classification:

235302

Abstract:

A program is developed for testing printed circuit boards by applying a proposed test program to a board which is initially in an arbitrary response state, comparing the resulting response pattern with a reference, modifying the proposed program if necessary to obtain a valid comparison, running the program on the board successively while faults are applied to selective board input nodes, determining penetration of the faults through the board by analyzing the toggle signatures of the response nodes, and again modifying the program if necessary. Circuit boards are tested with the resulting program by accumulating a running toggle signature number for selected response nodes as the program is applied to the test board, periodically sampling the numbers, and comparing the test samples with corresponding samples from a reference board. Defective board devices can then be traced and remedied; if a sampled defect persists, the test program is advanced in single step increments from the preceding sample until the defect is again detected. The board connections to the defective node may then be analyzed to pinpoint the defect.