Thomas A Willis

US Patent:

6728858, Apr 27, 2004

Filed:

Jun 27, 2001

Appl. No.:

09/894529

Inventors:

Thomas E. Willis - Mountain View CA
Achmed R. Zahir - Menlo Park CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

711206, 711147, 711150, 711152, 711207

Abstract:

A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Sharability of virtual address translations by logical processors may be determined by comparing page table physical base addresses of the logic processors. Using the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.

US Patent:

6858412, Feb 22, 2005

Filed:

Oct 24, 2001

Appl. No.:

09/999362

Inventors:

Thomas D. Willis - San Francisco CA, US
Paul Hardenbol - Los Altos CA, US
Maneesh Jain - Menlo Park CA, US
Viktor Stolc - Cupertino CA, US
Mostafa Ronaghi - Palo Alto CA, US
Ronald W. Davis - Palo Alto CA, US

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

C12P019/34
C12Q001/68
C07H021/02
C07H021/04

US Classification:

435 911, 435 6, 435 912, 536 243, 536 231

Abstract:

The invention is directed to novel methods of multiplexing nucleic acid reactions, including amplification, detection and genotyping. The invention relies on the use of precircle probes that are circularized in the presence of the corresponding target nucleic acids, cleaved, and then amplified.

US Patent:

6888551, May 3, 2005

Filed:

Dec 7, 2001

Appl. No.:

10/007923

Inventors:

Thomas E. Willis - Mountain View CA, US
Steven L. Midford - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/10

US Classification:

345568, 345545, 711202, 711206

Abstract:

A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided into tiles, which may be composed of one or more regions, and data in the frame buffer represents pixels on the display screen. When data representing a pixel is modified in the frame buffer, the region or tile associated with the pixel is marked as dirty, and those tiles or regions that are dirty in the frame buffer are written to the display.

US Patent:

6995756, Feb 7, 2006

Filed:

Mar 31, 2003

Appl. No.:

10/403144

Inventors:

Thomas E. Willis - Mountain View CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 5/00

US Classification:

345204, 345 98, 345100, 345691

Abstract:

A first pixel of a pixel array of a microdisplay is driven with a first pulse having a duration determined on the basis of a value loaded into a counter. A second pixel of the pixel array is driven with a second pulse having a duration determined on the basis of (a) the value loaded into the counter and (b) a value stored in a register.

US Patent:

6995771, Feb 7, 2006

Filed:

Dec 7, 2001

Appl. No.:

10/010524

Inventors:

Thomas E. Willis - Mountain View CA, US
Steven L. Midford - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 5/36

US Classification:

345545, 345531

Abstract:

A method, apparatus, and signal-bearing medium for sending to a display device modified regions of a frame buffer. A frame buffer is divided into the regions, and data in the frame buffer represents pixels on the display device. The frame buffer accumulates writes until the region being written to changes, at which time the region is copied to the display device.

US Patent:

7019884, Mar 28, 2006

Filed:

Mar 31, 2003

Appl. No.:

10/404958

Inventors:

Steven J. Kirch - Pleasanton CA, US
Kenneth E. Salsman - Pleasanton CA, US
Thomas E. Willis - Mountain View CA, US
Oleg Rashkovskiy - Cupertino CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G02B 26/00

US Classification:

359290, 349139

Abstract:

A spatial light modulator is adapted to receive bidirectional drive signals.

US Patent:

7038671, May 2, 2006

Filed:

Feb 22, 2002

Appl. No.:

10/081751

Inventors:

Thomas E. Willis - Mountain View CA, US
Michael O'Connor - Cupertino CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 5/00

US Classification:

345205, 345 87, 345208, 345690

Abstract:

Pulse-width modulation may be utilized to drive one or more display elements of a display (e. g. pixels of a liquid crystal display system) comprising a controller that supplies digital information including global and local digital information to a respective signal generator associated with each display element operably coupled to the controller for receiving the digital information. In one embodiment, a spatial light modulator includes a respective local drive circuit associated with each pixel of a pixel array, and a global drive circuit operably coupled to the pixel array for digitally driving the pixel electrodes. Each local drive circuit may include a pixel logic, a digital storage, and pulse-width modulation circuitry. The global drive circuit may include a control logic, and a memory storing global digital information indicative of a common reference (e. g. , a count value) and local digital information (e. g.

US Patent:

7038689, May 2, 2006

Filed:

Feb 19, 2002

Appl. No.:

10/079621

Inventors:

Thomas E. Willis - Mountain View CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 5/39

US Classification:

345531, 345539, 345545

Abstract:

A spatial light modulator having a double-buffering pixel value storage mechanism. A double-buffering mechanism enabling sparse refresh. A double-buffering value storage mechanism suitable for use with a serial or raster value producer and a value consumer, especially those in which it is desirable to consume an entire, completed frame or set of values at a time, and particularly those in which it is desirable to enable the producer to continue producing serially while the consumer is consuming in parallel fashion.