Thomas F Wolf

US Patent:

6559062, May 6, 2003

Filed:

Nov 15, 2000

Appl. No.:

09/713504

Inventors:

Stephen Ward Downey - Orlando FL
Allen Yen - Orlando FL
Thomas Michael Wolf - Orlando FL
Paul B. Murphey - Winter Garden FL

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L 21461

US Classification:

438734, 438754

Abstract:

A process ( ) for forming a metal interconnect ( ) in a semiconductor device ( ) using a photoresist layer ( ) having a thickness (T) of no more than 0. 66 microns without forming a notch in the side ( ) of the interconnect. A reactive ion etching process ( ) used to remove portions of a metal layer ( ) to form the interconnect includes a burst etch step ( ) wherein a first high flow rate ( ) of passivation gas is delivered, followed by a main metal etch step ( ) wherein the flow rate of passivation gas is reduced to a second lower value.

US Patent:

6985229, Jan 10, 2006

Filed:

May 30, 2002

Appl. No.:

10/158775

Inventors:

Cynthia C. Lee - Orlando FL, US
Stephen Arlon Meisner - St. Cloud FL, US
Thomas Michael Wolf - Orlando FL, US
Alberto Santoni - Orlando FL, US
John Martin McIntosh - Orlando FL, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

G01B 11/00
G01R 31/26
H01L 21/66

US Classification:

356401, 438 16

Abstract:

A method for nondestructively characterizing alignment overlay between two layers of a semiconductor wafer. An incident beam of radiation is directed upon the wafer surface and the properties of the resulting diffracted beam are determined, in one embodiment as a function of wavelength or incident angle. The spectrally or angularly resolved characteristics of the diffracted beam are related to the alignment of the overlay features. A library of calculated diffraction spectra is established by modeling a full range of expected variations in overlay alignment. The spectra resulting from the inspection of an actual wafer having alignment targets in at least two layers is compared against the library to identify a best fit to characterize the actual alignment. The results of the comparison may be used as an input for upstream and/or downstream process control.

US Patent:

7160799, Jan 9, 2007

Filed:

Jun 24, 2003

Appl. No.:

10/603041

Inventors:

Steven Alan Lytle - Orlando FL, US
Thomas Michael Wolf - Orlando FL, US
Allen Yen - Orlando FL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 21/4763

US Classification:

438637, 257E21579, 257E23151, 257E23169

Abstract:

The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.

US Patent:

57803161, Jul 14, 1998

Filed:

Jun 19, 1997

Appl. No.:

8/879109

Inventors:

Hongzong Chew - Orlando FL
John David Cuthbert - Orlando FL
Hamlet Herring - Orlando FL
John Louis Ryan - Hampton NJ
Robert Ching-I Sun - Orlando FL
Thomas Michael Wolf - Laurys Station PA
Daniel Mark Wroge - Orlando FL

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H01L 2100

US Classification:

438 11

Abstract:

Linewidth control features having integral transistors are disclosed. Optical and electrical measurements of the linewidth control feature and its associated transistor may be correlated thereby providing a method of improving production processes.