Thomas H Wolff

US Patent:

47232420, Feb 2, 1988

Filed:

Jun 27, 1986

Appl. No.:

6/879695

Inventors:

Brian R. Larson - Inver Grove Heights MN
Donald B. Bennett - Burnsville MN
Thomas O. Wolff - Fridley MN

Assignee:

Sperry Corporation - Blue Bell PA

International Classification:

G06F 1118

US Classification:

371 36

Abstract:

A digital system employing adaptive voting circuitry to improve its fault-tolerance receives an input data bit from each of a number of input data sources. The adaptive voting circuitry has a separate section for each of the input devices which has a weight register that stores an initial weight value which determines the voting strength of the associated input device. The weight values are multiplexed through to a voting circuit which also receives the input data bits. If an input data bit is a logic "1" the weight value of the input data device that supplied this "1" signal is added to the weight values of all other input data devices that supplied "1" data bits. If the data bit from a particular input device is a logic "0", then its weight is added to the weight values for other input data devices which supplied logic "0'". Accumulative voting then takes place via adders in the voting circuit which determines whether the correct output bit should be a logic "1" or a logic "0". After the correct output bit is obtained, it is compared with the input bits supplied by the different input data devices, and the stoned weight values associated with each of these are decremented if the input device supplied a data bit that did not conform to the correct output bit, or alternately they are incremented if it did.

US Patent:

40842266, Apr 11, 1978

Filed:

Sep 24, 1976

Appl. No.:

5/726701

Inventors:

Larry Don Anderson - Minneapolis MN
Thomas Ormond Wolff - Fridley MN
Leo John Slechta - Minneapolis MN

Assignee:

Sperry Rand Corporation - New York NY

International Classification:

G06F 920
G06F 1300

US Classification:

364200

Abstract:

A virtual address translator comprises a content addressed memory and a word addressed memory. A task name and subsegment number from a virtual address supplied by a processor are employed as a key word to search a content addressed memory and read out a subsegment descriptor if the key word is matched. The subsegment descriptor includes an absolute base address which is added to a deflection field to obtain an absolute memory address. The memory address is applied to a memory to permit transfer of a word between the processor and the memory. The processor may present any one of several task names depending upon whether the memory reference is made for an instruction or data for the processor, or for an instruction or data for an I/O connected to the processor. Bounds, residency and access privileges are checked using the subsegment descriptor. If a search of the content addressed memory reveals that the desired subsegment descriptor is not in the word addressed memory, the translator obtains the descriptor from memory and then generates the desired absolute memory address.

US Patent:

40965686, Jun 20, 1978

Filed:

Sep 24, 1976

Appl. No.:

5/726371

Inventors:

Donald Bruce Bennett - Burnsville MN
Leo John Slechta - Minneapolis MN
Thomas Ormond Wolff - Fridley MN

Assignee:

Sperry Rand Corporation - New York NY

International Classification:

G06F 920
G06F 1300

US Classification:

364200

Abstract:

A virtual address translator comprises a content addressed memory and a word addressed memory. A task name and subsegment number from a virtual address supplied by a processor are employed as a key word to search a content addressed memory and read out a subsegment descriptor if the key word is matched. The subsegment descriptor includes an absolute base address which is added to a deflection field to obtain an absolute memory address. The memory address is applied to a memory to permit transfer of a word between the processor and the memory. The processor may present any one of several task names depending upon whether the memory reference is made for an instruction or data for the processor, or for an instruction or data for an I/O connected to the processor. Bounds, residency and access privileges are checked using the subsegment descriptor. If a search of the content addressed memory reveals that the desired subsegment descriptor is not in the word addressed memory, the translator obtains the descriptor from memory and then generates the desired absolute memory address.