Thomas Alan Ziaja

US Patent:

7657805, Feb 2, 2010

Filed:

Jul 2, 2007

Appl. No.:

11/772328

Inventors:

Thomas Alan Ziaja - Austin TX, US
Kevin D. Woodling - Austin TX, US
Robert F. Molyneaux - Austin TX, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G01R 31/28

US Classification:

714724

Abstract:

An integrated circuit (IC) including a blocking pin. An IC may include state logic, a test control unit configured to coordinate access by external circuitry to operating state of the state logic during a test mode, and interface pins configured to couple the integrated circuit to the external circuitry. Shared interface pins may provide input signals to the test control unit during the test mode of operation and may perform distinct I/O functions during normal mode operation. A blocking interface pin, when asserted by external circuitry during normal mode operation, may force test signals derived from at least a portion of the shared interface pins by the test control unit into respective quiescent states, such that subsequent to assertion of the blocking pin, the integrated circuit is operable to enter the test mode of operation from the normal mode of operation without resetting operating state of the state logic.

US Patent:

7657807, Feb 2, 2010

Filed:

Jun 27, 2005

Appl. No.:

11/167248

Inventors:

Daniel R. Watkins - Saratoga CA, US
Hunter S. Donahue - Cupertino CA, US
Thomas Alan Ziaja - Austin TX, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G01R 31/28

US Classification:

714727, 714718, 714724, 714726

Abstract:

An integrated circuit including embedded test functionality. An integrated circuit may include a plurality of processor cores each configured to execute instructions, and a test access port configured to interface circuits included within the integrated circuit with a test environment external to the integrated circuit for testing of the circuits. The test access port may include virtualization logic configured to allow a first set of instructions executing on the given processor core to control activity of the test access port for testing of the circuits. In one embodiment, the circuits may be accessible for testing via a plurality of scan chains, wherein the scan chains and the test access port are compliant with a version of Joint Test Access Group (JTAG) standard IEEE 1149, and wherein the test access port includes a Test Data In (TDI) pin, a Test Data Out (TDO) pin, and a Test Clock (TCK) pin.

US Patent:

7795899, Sep 14, 2010

Filed:

Apr 8, 2009

Appl. No.:

12/420056

Inventors:

Gregory F. Grohoski - Bee Cave TX, US
Christopher H. Olson - Austin TX, US
Thomas Alan Ziaja - Pflugerville TX, US
Lawrence A. Spracklen - Boulder Creek CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

H03K 19/00

US Classification:

326 8, 326 9, 326 38

Abstract:

Systems and methods for enabling on-chip features via efuses. A system comprises an electronic fuse (Efuse) array (EFA) coupled to each features capability register (FCR) within an instantiated computational block. The EFA comprises a plurality of rows wherein programming an row comprises blowing one or more Efuses of the row. A valid row comprises programmed Efuses corresponding to one or more on-chip enabled features. The EFA is further configured to prevent enabling of disabled on-chip features from occurring subsequent to a predetermined point in time, such as the time of shipping the chip to the field for use by end-users, by establishing a particular default state for electronic fuses and rendering unusable any unprogrammed entries of the EFA. In one embodiment, some features correspond to on-chip hardware cryptographic acceleration. By preventing the ability to re-enable these features after shipping, it is possible to send semiconductor chips to foreign countries with only predetermined features enabled and no threat of disabled features being later enabled.

US Patent:

8065572, Nov 22, 2011

Filed:

Jun 30, 2009

Appl. No.:

12/495158

Inventors:

Thomas A. Ziaja - Austin TX, US
Murali Gala - San Jose CA, US
Paul J. Dickinson - San Jose CA, US
Karl P. Dahlgren - Evemont CA, US
David L. Curwen - Mountain View CA, US
Oliver Caty - Sunnyvale CA, US
Steven C. Krow-Lucal - Sunnyvale CA, US
James C. Hunt - Redwood City CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G11C 29/00
G01R 31/28

US Classification:

714718, 714719, 714720, 714726, 714727, 714729

Abstract:

An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.

US Patent:

8074133, Dec 6, 2011

Filed:

Aug 6, 2008

Appl. No.:

12/187145

Inventors:

Thomas A. Ziaja - Austin TX, US
Kevin D. Woodling - Austin TX, US
Robert F. Molyneaux - Austin TX, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G01R 31/28

US Classification:

714731

Abstract:

An apparatus or method for testing of a SOC processor device may minimize interference that is caused by interfacing a comparatively low-speed testing device with the high-speed processor during testing. Implementations may gate the input clock signal at the clock input to each domain of the SOC processor device rather than at the output of the PLL clock. The gating of the clock signal to each domain may then be controlled by clock stop signals generated by the testing device and sent to the individual domains of the processor device. Gating the clock signal at the domain may provide a more natural state for the circuit during testing as well as allow the test control unit to test the different domains of the SOC device individually.

US Patent:

8214703, Jul 3, 2012

Filed:

Mar 10, 2009

Appl. No.:

12/401354

Inventors:

Murali Mohan Reddy Gala - San Jose CA, US
Olivier Francis Cyrille Caty - Sunnyvale CA, US
Thomas Alan Ziaja - Austin TX, US
Paul Dickinson - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G01R 31/28
G06F 11/00

US Classification:

714729, 714 30, 714726, 714736

Abstract:

Methods and apparatuses are disclosed for testing multicore processors. In some embodiments, the tested multicore processor may include at least a first core and a second core, a data input coupled to a first scan chain in the first core and a second scan chain in the second core, and a multiplexer including at least a first input and a second input, the first input coupled with a data output of the first scan chain and the second input coupled with a data output of the second scan chain, the multiplexer further including an output that couples to one or more pins on a package of the processor, the multiplexer further including a select signal that couples to the one or more pins on the package of the processor, and wherein the data input couples to the one or more pins on the package of the processor.

US Patent:

20030076723, Apr 24, 2003

Filed:

Oct 24, 2001

Appl. No.:

10/039498

Inventors:

Kamran Zarrineh - Nashua NH, US
Thomas Ziaja - Austin TX, US
Amitava Majumdar - San Jose CA, US

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G11C007/00

US Classification:

365/201000

Abstract:

Methods and systems for automated memory test modeling generation and validation are provided. Information supplied by a graphical user interface is used to generate a customized memory primitive. The memory primitive subsequently undergoes a two phase validation to test for correct functioning.