Tien Ryan Pham

US Patent:

7256612, Aug 14, 2007

Filed:

Jun 14, 2005

Appl. No.:

11/151796

Inventors:

Steven P. Young - Boulder CO, US
Tien Pham - San Jose CA, US
Philip D. Costello - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/173
H03K 19/177
G06F 7/38
H01L 25/00

US Classification:

326 41, 326 37, 326 38, 326 39, 326 40, 326 47, 326 93

Abstract:

A programmable logic block provides programmable initialization values for carry chains traversing the logic block, without consuming user logic resources. An exemplary programmable logic block includes two or more carry multiplexers coupled together to form a carry chain for the programmable logic block. A carry initialization circuit has an output terminal coupled to a data input terminal of a first carry multiplexer in the carry chain. The carry initialization circuit is controlled by configuration memory cells of the programmable logic block to select one of a carry in signal, a power high signal, a ground signal, and (optionally) a signal from an interconnect structure of the logic block. Thus, an initialization value (e. g. , power high or ground) can be provided to the carry chain without consuming other programmable resources within the logic block.

US Patent:

7436208, Oct 14, 2008

Filed:

Jul 17, 2006

Appl. No.:

11/487916

Inventors:

Tien Duc Pham - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38
H03K 19/173
H03K 19/0175

US Classification:

326 38, 326 37, 326 62

Abstract:

A carry circuit having a power-save mode and a method for reducing power consumption of an integrated circuit are described. A power-save input is selected for control select signaling. A voltage level input is selected as an initial carry input. The initial carry input is propagated through a carry stage responsive to the carry input and the control select signaling. The carry stage is placed in a first non-switching steady state mode responsive to the propagating of the initial carry input through the carry stage.

US Patent:

8228102, Jul 24, 2012

Filed:

Mar 3, 2010

Appl. No.:

12/717062

Inventors:

Tien Duc Pham - San Jose CA, US
Richard G. Cliff - Los Altos CA, US
Tim Tri Hoang - San Jose CA, US
Weiqi Ding - Fremont CA, US
Sriram Narayan - Pleasanton CA, US
Thungoc M. Tran - San Jose CA, US
Kumara Tharmalingam - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03L 7/06

US Classification:

327156, 327141, 327147

Abstract:

One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.

US Patent:

8294500, Oct 23, 2012

Filed:

Nov 18, 2009

Appl. No.:

12/621493

Inventors:

Vinh Van Ho - San Jose CA, US
Tien Duc Pham - San Jose CA, US
Tim Tri Hoang - San Jose CA, US
Van Ton-That - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03H 11/16

US Classification:

327231, 327237

Abstract:

A phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.

US Patent:

8537956, Sep 17, 2013

Filed:

Nov 24, 2010

Appl. No.:

12/954514

Inventors:

Tien Duc Pham - San Jose CA, US
Leon Zheng - San Francisco CA, US
Zhi Y. Wong - San Jose CA, US
Paul B. Ekas - Redwood City CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03D 3/24

US Classification:

375376, 375373, 375371, 375354, 375316

Abstract:

A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.

US Patent:

8542042, Sep 24, 2013

Filed:

Jun 25, 2012

Appl. No.:

13/532528

Inventors:

Tien Duc Pham - San Jose CA, US
Richard G. Cliff - Los Altos CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03L 7/06

US Classification:

327156, 327155, 327158, 327161

Abstract:

One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

US Patent:

8619931, Dec 31, 2013

Filed:

Nov 19, 2009

Appl. No.:

12/622152

Inventors:

Tien Duc Pham - San Jose CA, US
Tim Tri Hoang - San Jose CA, US
Thungoc M. Tran - San Jose CA, US
Vinh Van Ho - San Jose CA, US
Leon Zheng - San Francisco CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H04L 7/00

US Classification:

375355

Abstract:

Integrated circuits having transceivers capable of high-speed (e. g. , 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.

US Patent:

7268587, Sep 11, 2007

Filed:

Jun 14, 2005

Appl. No.:

11/152012

Inventors:

Tien Pham - San Jose CA, US
Manoj Chirania - Palo Alto CA, US
Venu M. Kondapalli - Sunnyvale CA, US
Steven P. Young - Boulder CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 25/00
H03K 19/177

US Classification:

326 41, 326 38, 326 47

Abstract:

A programmable logic block provides N-bit and M-bit (e. g. , (N/2)-bit) lookahead functionality for carry chains traversing the logic block, N and M being integers greater than one. An exemplary programmable logic block includes four carry multiplexers that together form a 4-bit lookahead carry chain. The 4-bit lookahead carry chain also provides a 2-bit lookahead output after the second carry multiplexer. Alternatively, the last two bits of the 4-bit lookahead carry chain can be used as a 2-bit lookahead carry chain. In one embodiment, the programmable logic block also includes four function generators associated with the four carry multiplexers. Each function generator drives a select terminal of the associated carry multiplexer. The 4-bit and 2-bit carry chains can be programmably coupled to an interconnect structure of the PLD at the carry out output terminals. In some embodiments, an initialization value can also be provided to the 4-bit and 2-bit carry chains.