Timothy M Dobbins

US Patent:

57614440, Jun 2, 1998

Filed:

Sep 5, 1995

Appl. No.:

8/523385

Inventors:

Jasmin Ajanovic - Folsom CA
Robert N. Murdoch - Sacramento CA
Timothy M. Dobbins - Folsom CA
Aditya Sreenivas - Folsom CA
Stuart E. Sailer - Folsom CA
Jeffrey L. Rabe - Rancho Cordova CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1336

US Classification:

395280

Abstract:

A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

US Patent:

57064440, Jan 6, 1998

Filed:

Jan 24, 1996

Appl. No.:

8/590954

Inventors:

Timothy M. Dobbins - Folsom CA
Zohar Bogin - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

395280

Abstract:

A semiconductor component which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component comprises of a first signal generator capable of sending a signal of a first type over a shared line and a second signal generator capable of sending a signal of a second type over the line. It also comprises of a first logic device capable of controlling the first signal generator and a second logic device capable of controlling the second signal generator.

US Patent:

55332005, Jul 2, 1996

Filed:

Mar 18, 1994

Appl. No.:

8/210560

Inventors:

Timothy M. Dobbins - Folsom CA
Zohar Bogin - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

395280

Abstract:

A semiconductor component is which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component comprises of a first signal generator capable of sending a signal of a first type over a shared line and a second signal generator capable of sending a signal of a second type over the line. It also comprises of a first logic device capable of controlling the first signal generator and a second logic device capable of controlling the second signal generator.

US Patent:

59744880, Oct 26, 1999

Filed:

Aug 28, 1997

Appl. No.:

8/919387

Inventors:

Timothy M. Dobbins - Folsom CA
Zohar Bogin - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710100

Abstract:

A semiconductor component is described which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component comprises of a first signal generator capable of sending a signal of a first type over a shared line and a second signal generator capable of sending a signal of a second type over the line. It also comprises of a first logic device capable of controlling the first signal generator and a second logic device capable of controlling the second signal generator.