Timothy P Dunham

US Patent:

7051307, May 23, 2006

Filed:

Dec 3, 2003

Appl. No.:

10/707286

Inventors:

Gary S. Ditlow - Garrison NY, US
Daria R. Dooling - Huntington VT, US
Timothy G. Dunham - South Burlington VT, US
William C. Leipold - Enosburg Falls VT, US
Stephen D. Thomas - Essex Junction VT, US
Ralph J. Williams - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 7

Abstract:

Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.