Timothy J Sullivan

US Patent:

6417572, Jul 9, 2002

Filed:

Jul 16, 1999

Appl. No.:

09/354592

Inventors:

Dureseti Chidambarrao - Weston CT
Ronald G. Filippi - Wappingers Falls NY
Robert Rosenberg - Cortlandt Manor NY
Thomas M. Shaw - Peekskill NY
Timothy D. Sullivan - Underhill VT
Richard A. Wachnik - Mount Kisco NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257773, 257775, 257765

Abstract:

A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced. The process is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.

US Patent:

6876282, Apr 5, 2005

Filed:

May 17, 2002

Appl. No.:

10/150285

Inventors:

Panayotis Constantinou Andricacos - Croton-on-Hudson NY, US
L. Paivikki Buchwalter - Hopewell Junction NY, US
Hariklia Deligianni - Tenafly NJ, US
Robert A. Groves - Highland NY, US
Christopher Jahnes - Upper Saddle River NJ, US
Jennifer L. Lund - Brookeville MD, US
Michael Meixner - Erlangen, DE
David Earle Seeger - Congers NY, US
Timothy D. Sullivan - Underhill VT, US
Ping-Chuan Wang - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01H051/22

US Classification:

335 78, 200181

Abstract:

A microelectromechanical switch including: at least one pair of actuator electrodes; at least one input electrode and at least one output electrode for input and output, respectively, of a radio frequency signal; and a beam movable by an attraction between the at least one pair of actuator electrodes, the movable beam having at least a portion electrically connected to the at least one input electrode and to the at least one output electrode when moved by the attraction between the at least one pair of actuator electrodes to make an electrical connection between the at least one input and output electrodes; wherein the at least one pair of actuator electrodes are electrically isolated from each of the at least one input and output electrodes. The microelectromechanical switch can be configured in single or multiple-poles and/or single or multiple throws.

US Patent:

6992390, Jan 31, 2006

Filed:

Nov 7, 2003

Appl. No.:

10/702651

Inventors:

Daniel C. Edelstein - White Plains NY, US
Baozhen Li - South Burlington VT, US
Timothy D. Sullivan - Underhill VT, US

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257752, 257750, 257751

Abstract:

An interconnection structure for semiconductor integrated circuits is disclosed. The interconnection structure comprises a redundant layer, and at least one adhesion/diffusion barrier layer. The redundant layer comprises a metal or metal alloy selected from Ta, Mo, W, Be, Cr, Co, Ir, Ni, Nb, Os, Pd, Pt, Rb, Rh, Ru, and Th.

US Patent:

6995392, Feb 7, 2006

Filed:

Aug 7, 2002

Appl. No.:

10/214546

Inventors:

Paul S. McLaughlin - Poughkeepsie NY, US
Timothy D. Sullivan - Underhill VT, US
Ping-Chuan Wang - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/58

US Classification:

257 48

Abstract:

A test structure is disclosed for locating electromigration voids in a semiconductor interconnect structure having an interconnect via interconnecting a lower metallization line with an upper metallization line. In an exemplary embodiment, the test structure includes a via portion the top of the interconnect via at the upper metallization line. In addition, a line portion extends from the via portion, wherein the line portion connects to an external probing surface, in addition to a probing surface on the lower metallization line, thereby allowing the identification of any electromigration voids present in the interconnect via.

US Patent:

7212091, May 1, 2007

Filed:

Feb 8, 2005

Appl. No.:

11/053732

Inventors:

Panayotis Constantinou Andricacos - Croton-on-Hudson NY, US
L. Paivikki Buchwalter - Hopewell Junction NY, US
Hariklia Deligianni - Tenafly NJ, US
Robert A. Groves - Highland NY, US
Christopher Jahnes - Upper Saddle River NJ, US
Jennifer L. Lund - Brookeville MD, US
Michael Meixner - Erlangen, DE
David Earle Seeger - Congers NY, US
Timothy D. Sullivan - Underhill VT, US
Ping-Chuan Wang - Hopewell Junction NY, US

Assignee:

International Business Machines Coproration - Armonk NY

International Classification:

H01H 51/22

US Classification:

335 78, 200181

Abstract:

A microelectromechanical switch including: at least one pair of actuator electrodes; at least one input electrode and at least one output electrode for input and output, respectively, of a radio frequency signal; and a beam movable by an attraction between the at least one pair of actuator electrodes, the movable beam having at least a portion electrically connected to the at least one input electrode and to the at least one output electrode when moved by the attraction between the at least one pair of actuator electrodes to make an electrical connection between the at least one input and output electrodes; wherein the at least one pair of actuator electrodes are electrically isolated from each of the at least one input and output electrodes. The microelectromechanical switch can be configured in single or multiple-poles and/or single or multiple throws.

US Patent:

7224063, May 29, 2007

Filed:

Jun 1, 2001

Appl. No.:

09/871883

Inventors:

Birendra N. Agarwala - Hopewell Junction NY, US
Eric M. Coker - Burlington VT, US
Anthony Correale, Jr. - Raleigh NC, US
Hazara S. Rathore - Stormville NY, US
Timothy D. Sullivan - Underhill VT, US
Richard A. Wachnik - Mount Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/52

US Classification:

257758, 257753, 257767, 257773, 257E23142, 257E23145

Abstract:

An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

US Patent:

7397260, Jul 8, 2008

Filed:

Nov 4, 2005

Appl. No.:

11/163948

Inventors:

Kaushik Chanda - Fishkill NY, US
Birendra Agarwala - Hopewell Junction NY, US
Lawrence A. Clevenger - La Grangeville NY, US
Andrew P. Cowley - Wappingers Falls NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Jason P. Gill - Essex Junction VT, US
Tom C. Lee - Essex Junction VT, US
Baozhen Li - South Burlington VT, US
Paul S. McLaughlin - Poughkeepsie NY, US
Du B. Nguyen - Danbury CT, US
Hazara S. Rathore - Stormville NY, US
Timothy D. Sullivan - Underhill VT, US
Chih-Chao Yang - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/02
H01L 23/58
G01N 25/20

US Classification:

324763, 257 48, 374 57

Abstract:

A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

US Patent:

7470613, Dec 30, 2008

Filed:

Jan 4, 2007

Appl. No.:

11/619748

Inventors:

Birendra N. Agarwala - Hopewell Junction NY, US
Eric M. Coker - Burlington VT, US
Anthony Correale, Jr. - Raleigh NC, US
Hazara S. Rathore - Stormville NY, US
Timothy D. Sullivan - Underhill VT, US
Richard A. Wachnik - Mount Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438627, 257E21579, 438622

Abstract:

A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.