Ting Ting Chang

US Patent:

20210399002, Dec 23, 2021

Filed:

Jun 23, 2020

Appl. No.:

16/910020

Inventors:

- Santa Clara CA, US
Walid M. HAFEZ - Portland OR, US
Rohan BAMBERY - Hillsboro OR, US
Daniel B. O'Brien - Beaverton OR, US
Christopher Alan NOLPH - Hillsboro OR, US
Rahul RAMASWAMY - Portland OR, US
Ting CHANG - Portland OR, US

International Classification:

H01L 27/11568
H01L 49/02
H01L 29/78
H01L 29/792
H01L 21/28
H01L 29/66

Abstract:

Embodiments disclosed herein include a semiconductor device and methods of forming such a device. In an embodiment, the semiconductor device comprises a substrate and a transistor on the substrate. In an embodiment, the transistor comprises a first gate electrode, where the first gate electrode is part of a first array of gate electrodes with a first pitch. In an embodiment, the first gate electrode has a first average grain size. In an embodiment, the semiconductor device further comprises a component cell on the substrate. In an embodiment, the component cell comprises a second gate electrode, where the second gate electrode is part of a second array of gate electrodes with a second pitch that is larger than the first pitch. In an embodiment, the second gate electrode has a second average grain size that is larger than the first average grain size.

US Patent:

20210280683, Sep 9, 2021

Filed:

Mar 5, 2020

Appl. No.:

16/810156

Inventors:

- Santa Clara CA, US
Rahul RAMASWAMY - Portland OR, US
Jeong Dong KIM - Scappoose OR, US
Babak FALLAHAZAD - Portland OR, US
Ting CHANG - Portland OR, US
Nidhi NIDHI - Hillsboro OR, US
Walid M. HAFEZ - Portland OR, US

International Classification:

H01L 29/423
H01L 29/06
H01L 29/66
H01L 29/165
H01L 29/10
H01L 21/02

Abstract:

Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

US Patent:

20210257452, Aug 19, 2021

Filed:

Feb 19, 2020

Appl. No.:

16/795081

Inventors:

- Santa Clara CA, US
Jeong Dong KIM - Scappoose OR, US
Walid M. HAFEZ - Portland OR, US
Rahul RAMASWAMY - Portland OR, US
Ting CHANG - Portland OR, US
Babak FALLAHAZAD - Portland OR, US

International Classification:

H01L 29/06
H01L 29/10
H01L 27/088
H01L 29/423
H01L 29/08
H01L 21/8234

Abstract:

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

US Patent:

20210257453, Aug 19, 2021

Filed:

May 5, 2021

Appl. No.:

17/308900

Inventors:

- Santa Clara CA, US
Jeong Dong KIM - Scappoose OR, US
Walid M. HAFEZ - Portland OR, US
Rahul RAMASWAMY - Portland OR, US
Ting CHANG - Portland OR, US
Babak FALLAHAZAD - Portland OR, US

International Classification:

H01L 29/06
H01L 29/423
H01L 29/10
H01L 29/08
H01L 27/088

Abstract:

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

US Patent:

20190097057, Mar 28, 2019

Filed:

Nov 29, 2018

Appl. No.:

16/203780

Inventors:

- Santa Clara CA, US
Chia-Hong Jan - Portland OR, US
Walid M. Hafez - Portland OR, US
Ting Chang - Hillsboro OR, US
Rahul Ramaswamy - Hillsboro OR, US
Pei-Chi Liu - Portland OR, US

International Classification:

H01L 29/78
H01L 21/8234
H03D 7/16

Abstract:

An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

US Patent:

20170207312, Jul 20, 2017

Filed:

Aug 19, 2014

Appl. No.:

15/327641

Inventors:

- Santa Clara CA, US
Walid Hafez - Portland OR, US
Ting Chang - Portland OR, US
Rahul Ramaswamy - Hillsboro OR, US
Pei-Chi Liu - Portland OR, US
Neville Dias - Hillsboro OR, US

International Classification:

H01L 29/423
H01L 23/66
H01L 21/8234
H01L 27/088
H01L 23/535

Abstract:

Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

US Patent:

20170162503, Jun 8, 2017

Filed:

Aug 19, 2014

Appl. No.:

15/327338

Inventors:

- Santa Clara CA, US
Walid HAFEZ - Portland OR, US
Chia-Hong JAN - Portland OR, US
Ting CHANG - Portland OR, US
Rahul RAMASWAMY - Hillsboro OR, US
Pei-Chi LIU - Portland OR, US
Neville DIAS - Hillsboro OR, US

International Classification:

H01L 23/525
H01L 29/78
H01L 29/423
H01L 21/768

Abstract:

A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

US Patent:

20170098709, Apr 6, 2017

Filed:

Jun 27, 2014

Appl. No.:

15/127850

Inventors:

- Santa Clara CA, US
CHIA-HONG JAN - Portland OR, US
WALID M. HAFEZ - Portland OR, US
TING CHANG - Hillsboro OR, US
RAHUL RAMASWAMY - Hillsboro OR, US
PEI-CHI LIU - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/78
H01L 29/10
H03D 7/14
H01L 29/08
H01L 21/8234
H01L 27/088
H01L 29/06

Abstract:

An embodiment includes an apparatus comprising: a non-planar fm having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one fmFET. Other embodiments are described herein.