Ting C Lu

US Patent:

8161212, Apr 17, 2012

Filed:

Sep 22, 2010

Appl. No.:

12/888333

Inventors:

Ting Lu - Austin TX, US
Kam-Wing Li - Cupertino CA, US
Bradley L. Taylor - Santa Cruz CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 13/12
G06F 3/00
G06F 1/12

US Classification:

710 71, 710 20, 710 33, 710 36, 713400, 713500, 713600

Abstract:

An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be configured to store a data unit specified by the source request. The system can include an I/O device controller coupled to the interface. The I/O device controller can be configured to correlate the source request with a plurality of I/O device requests and initiate sending of the plurality of I/O device requests to the plurality of non-volatile I/O devices in parallel. The system also can include a decoder coupled to the first memory and the I/O device controller. The decoder can be configured to receive data from the plurality of non-volatile I/O devices in parallel.

US Patent:

8248883, Aug 21, 2012

Filed:

Aug 31, 2010

Appl. No.:

12/873041

Inventors:

Ting Lu - Austin TX, US
Kam-Wing Li - Cupertino CA, US
Anatoly Belkin - Glenview IL, US
Ahmad R. Ansari - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G11C 8/00

US Classification:

36523006, 36523001

Abstract:

A system for implementing a non-volatile input/output (I/O) device based memory can include an interface configured to receive a processor request specifying a data unit. The data unit can be specified by a processor address. The system can include an address-data converter coupled to the interface. The address-data converter can be configured to correlate the processor address of the data unit to a data block within the non-volatile I/O device. The system further can include an I/O controller coupled to the address-data converter. The I/O controller can be configured to issue a non-volatile I/O device command specifying the data block to the non-volatile I/O device.

US Patent:

8443129, May 14, 2013

Filed:

Jul 21, 2010

Appl. No.:

12/841013

Inventors:

James J. Murray - Los Gatos CA, US
Ting Lu - Austin TX, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 13/12

US Classification:

710307, 710 66

Abstract:

A data bus interface channel controller circuit for an N-bit data bus is described. A FIFO command queue is coupled to receive and buffer one or more commands formatted for M-bit transactions. A FIFO data queue is coupled to receive and buffer N-bit formatted data packets. A first translation circuit is coupled to the FIFO command queue and configured to translate the each commands into a selected one of a plurality of transaction formats. A transmission control circuit is coupled and configured to receive and transmit commands removed from the FIFO command queue. The transmission control circuit is configured to track a number of outstanding transmitted commands and, in response to receiving a command having a transaction format different from the previously received command, delay transmission of commands on the N-bit data bus until the number of outstanding transmitted commands equals zero.

US Patent:

8595561, Nov 26, 2013

Filed:

Oct 27, 2010

Appl. No.:

12/913713

Inventors:

Ting Lu - Austin TX, US
Robert L. Pelt - San Jose CA, US
Bradley L. Taylor - Santa Cruz CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 11/00

US Classification:

714 45, 714 25

Abstract:

A method of debugging within an integrated circuit (IC) that includes an embedded processor can include detecting an event within a circuit of the IC that is external to the processor and, responsive to detecting the event, initiating a debug function within the processor. Similarly, responsive to detecting an event within the processor, a debug function within a circuit block of the IC that is external to the processor can be initiated. Trace data generated within the processor and trace data generated within the programmable fabric further can be merged to generate combined trace data.

US Patent:

8612789, Dec 17, 2013

Filed:

Jan 13, 2011

Appl. No.:

13/005994

Inventors:

Bradley L. Taylor - Santa Cruz CA, US
Ting Lu - Austin TX, US
William E. Allaire - West Chester PA, US
Hassan K. Bazargan - Saratoga CA, US
Hy V. Nguyen - San Jose CA, US
Shashank Bhonge - Bangalore, IN

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 1/26

US Classification:

713324

Abstract:

An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.

US Patent:

20120185674, Jul 19, 2012

Filed:

Jan 13, 2011

Appl. No.:

13/005962

Inventors:

Bradley L. Taylor - Santa Cruz CA, US
Ting Lu - Austin TX, US

Assignee:

XILINX, INC. - San Jose CA

International Classification:

G06F 15/76
G06F 9/30

US Classification:

712 37, 712E09016

Abstract:

A method of extending a processor system within an integrated circuit (IC) can include executing program code within the processor system implemented within the IC, wherein the IC includes a programmable fabric. The processor system further can be coupled to the programmable fabric. A process can be performed using a process-specific circuit implemented within the programmable fabric in lieu of using the processor system. A result of the process from the process-specific circuit can be made available to the processor system.

US Patent:

20120221833, Aug 30, 2012

Filed:

Feb 28, 2011

Appl. No.:

13/037234

Inventors:

William E. Allaire - West Chester PA, US
Bradley L. Taylor - Santa Cruz CA, US
Ting Lu - Austin TX, US
Sandeep Dutta - Foster City CA, US
Patrick J. Crotty - San Jose CA, US
Hassan K. Bazargan - Saratoga CA, US
Hy V. Nguyen - San Jose CA, US
Shashank Bhonge - Bangalore, IN

Assignee:

XILINX, INC. - San Jose CA

International Classification:

G06F 15/76
G06F 9/06

US Classification:

712 37, 712E09003

Abstract:

An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

US Patent:

7958414, Jun 7, 2011

Filed:

Sep 22, 2010

Appl. No.:

12/888317

Inventors:

Ahmad R. Ansari - San Jose CA, US
Ting Lu - Austin TX, US
Ismed D. Hartanto - Castro Valley CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 31/28
G11C 29/00
G11C 7/00
H03K 19/00
G06F 7/38

US Classification:

714718, 714719, 714725, 365201, 365222, 326 8, 326 39

Abstract:

An embodiment of a method of enhancing security of internal memory is disclosed. For this embodiment of the method, the application specific block is operated in a functional mode, and a reset of the application specific block is initiated. From a built-in self-test engine, at least one write to the internal memory is initiated in response to the reset initiated, where the at least one write overwrites data stored in the internal memory during a reset mode.