Toan T Tran

US Patent:

6598132, Jul 22, 2003

Filed:

Jul 18, 2001

Appl. No.:

09/908616

Inventors:

Toan D. Tran - Sunnyvale CA
Robert J. Divivier - San Jose CA
Siyad Ma - Palo Alto CA

Assignee:

Zettacom, Inc. - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711154, 711122

Abstract:

A traffic manager for a network switch port includes a buffer memory and a buffer manager for writing incoming cells into the buffer memory and for thereafter reading the cells out of the buffer memory and forwarding them. The traffic manager also includes a queue manager for determining an order in which the buffer manager is to forward a set of cells stored in the buffer memory. The queue manager supplies the buffer manager with a sequence of pointers, each pointer referencing a separate cell of the set of cells, with the sequence of pointers being ordered to indicate an order in which the buffer manager is to forward the set of cells. After receiving the pointer sequence, the buffer manager changes the order of pointers in the pointer sequence to optimize a rate at which it can read the cells out of the buffer memory. The buffer manager reads the cells out of the buffer memory in an order indicated by the changed pointer sequence and thereafter forwards the cells read out of the buffer memory in the order in which the queue manager determined the cells are to be forwarded.

US Patent:

7058070, Jun 6, 2006

Filed:

May 1, 2001

Appl. No.:

09/847079

Inventors:

Toan D. Tran - Sunnyvale CA, US
Robert J. Divivier - San Jose CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

H04L 12/28

US Classification:

370412, 370419, 370429

Abstract:

A network switch port includes a cell memory, a queuing system, a data path controller and an output buffer. The data path controller stores incoming cells derived from network data transmissions in the cell memory. The queuing system generates the cell memory address of each stored cell when the cell is to be forwarded from the cell memory, and the data path controller appends the cell memory address of that cell to a linked list of addresses of cells to be forwarded from the memory. When the linked list is not empty, the data path controller forwards cells from the cell memory to the output buffer in the order that their cell memory addresses were appended to the linked list. The output buffer stores and then sequentially forwards the cells outward from the switch port to a receiving network component which store them in a cell buffer until it can forward them elsewhere. The receiving network component produces a multiple bit back pressure data indicating how much of its cell buffer is currently filled with cells. Depending on the fill amount the back pressure data indicates, the output buffer either halts or continues to forward cells to the receiving network component, and either halts or continues allowing the data path controller to forward cells from the cell memory to the output buffer.

US Patent:

7989365, Aug 2, 2011

Filed:

Aug 18, 2009

Appl. No.:

12/543245

Inventors:

Soonam Park - Mountain View CA, US
Soo Jeon - San Jose CA, US
Toan Q. Tran - San Jose CA, US
Qiwei Liang - Fremont CA, US
Dmitry Lubomirsky - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/316

US Classification:

438788, 438792, 438905, 257E21278, 427574

Abstract:

Methods of seasoning a remote plasma system are described. The methods include the steps of flowing a silicon-containing precursor into a remote plasma region to deposit a silicon containing film on an interior surface of the remote plasma system. The methods reduce reactions with the seasoned walls during deposition processes, resulting in improved deposition rate, improved deposition uniformity and reduced defectivity during subsequent deposition.

US Patent:

8181140, May 15, 2012

Filed:

Nov 9, 2009

Appl. No.:

12/615173

Inventors:

Vassili Kireev - Sunnyvale CA, US
James Karp - Saratoga CA, US
Toan D. Tran - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716122, 716123, 716129, 716130, 716132

Abstract:

A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted.

US Patent:

8436642, May 7, 2013

Filed:

Aug 23, 2011

Appl. No.:

13/216093

Inventors:

Vassili Kireev - Sunnyvale CA, US
Toan D. Tran - San Jose CA, US

Assignee:

XIlinx, Inc. - San Jose CA

International Classification:

H03K 17/16

US Classification:

326 30, 326 38, 326 86, 327108

Abstract:

An integrated circuit device includes an input/output (IO) pad, and a programmable termination capacitance circuit coupled to the IO pad, the programmable termination capacitance circuit comprising at least one compensation bank, wherein each of the at least one compensation bank includes a compensation capacitor coupled to a reference voltage through a compensation pass gate.

US Patent:

8453092, May 28, 2013

Filed:

Apr 6, 2012

Appl. No.:

13/441809

Inventors:

Vassili Kireev - Sunnyvale CA, US
James Karp - Saratoga CA, US
Toan D. Tran - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50
H03K 19/00
H03K 25/00
H01F 21/02
H01F 29/00
H03K 19/0175
H03K 19/003
H01F 27/28
H01L 25/07
H01L 25/16

US Classification:

716120, 716119, 716122, 716123, 716129, 716130, 326 38, 326101, 336 15, 336 69, 336 70

Abstract:

An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.

US Patent:

20190362944, Nov 28, 2019

Filed:

Aug 9, 2019

Appl. No.:

16/537048

Inventors:

- Santa Clara CA, US
Hideo Sugai - Kasugai-shi, JP
Nikolai Kalnin - Pleasanton CA, US
Soonam Park - Sunnyvale CA, US
Toan Tran - San Jose CA, US
Dmitry Lubomirsky - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01J 37/32
H01L 21/67

Abstract:

A system includes a process chamber, a housing that defines a waveguide cavity, and a first conductive plate within the housing. The first conductive plate faces the process chamber. The system also includes one or more adjustment devices that can adjust at least a position of the first conductive plate, and a second conductive plate, coupled with the housing, between the waveguide cavity and the process chamber. Electromagnetic radiation can propagate from the waveguide cavity into the process chamber through apertures in the second conductive plate. The system also includes a dielectric plate that seals off the process chamber from the waveguide cavity, and one or more electronics sets that transmit the electromagnetic radiation into the waveguide cavity. A plasma forms when at least one process gas is within the chamber, and the electromagnetic radiation propagates into the process chamber from the waveguide cavity.

US Patent:

20190304756, Oct 3, 2019

Filed:

Apr 3, 2019

Appl. No.:

16/374420

Inventors:

- Santa Clara CA, US
Soonam Park - Sunnyvale CA, US
Toan Q. Tran - San Jose CA, US
Lili Ji - San Jose CA, US
Dmitry Lubomirsky - Cupertino CA, US
Akhil Devarakonda - San Jose CA, US
Tien Fak Tan - Campbell CA, US
Tae Won Kim - San Jose CA, US
Saravjeet Singh - Sunnyvale CA, US
Alexander Tam - Union City CA, US
Jingchun Zhang - Cupertino CA, US
Jing J. Zhang - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01J 37/32
C23C 4/134
C23C 4/11

Abstract:

Systems and methods may be used to produce coated components. Exemplary chamber components may include an aluminum, stainless steel, or nickel plate defining a plurality of apertures. The plate may include a hybrid coating, and the hybrid coating may include a first layer comprising a corrosion resistant coating. The first layer may extend conformally through each aperture of the plurality of apertures. The hybrid coating may also include a second layer comprising an erosion resistant coating extending across a plasma-facing surface of the semiconductor chamber component.