Toan Van Tran

US Patent:

7204888, Apr 17, 2007

Filed:

May 1, 2003

Appl. No.:

10/428967

Inventors:

Toan Q. Tran - San Jose CA, US
Daniel S. Herkalo - San Jose CA, US
Jin Ho Lee - Suwon Kyunggi, KR
Dong Hyung Lee - Suwon Kyunggi, KR
Jang Seok Oh - Suwon Kyunggi, KR
Won B. Bang - Santa Clara CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 16/00
C23F 1/00
H01L 21/306

US Classification:

118728, 15634551, 15634552, 15634553, 15634554, 15634555, 118729, 118730

Abstract:

Embodiments of the present invention provide an apparatus for constraining and supporting the lift pins to prevent or minimize lateral movement of the lift pins that causes substrate hand-off problems and associated degradation in substrate processing characteristics and results. In one embodiment, a lift pin assembly for manipulating a substrate above a support surface of a substrate support comprises a plurality of lift pins movable between an up position and a down position. The lift pins include top ends and bottom ends. The top ends are configured to be lifted above the support surface of the substrate support to contact a bottom surface of the substrate in the up position. The top ends are configured to be positioned at or below the support surface of the substrate support in the down position. A lift pin connecting member is attached to the plurality of lift pins at attachment locations at or near the bottom ends of the lift pins to maintain fixed relative distances between the lift pins at the attachment locations and to move with the lift pins between the up position and the down position.

US Patent:

7806383, Oct 5, 2010

Filed:

Jun 1, 2007

Appl. No.:

11/756632

Inventors:

Toan Q. Tran - San Jose CA, US
Lun Tsuei - Mountain View CA, US
Won Bang - Gilroy CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

F16K 25/00

US Classification:

251193, 251175, 251328

Abstract:

Embodiments of a valve assembly for a process chamber having improved seal performance are provided herein. In some embodiments, a valve assembly for a process chamber includes a housing having an opening disposed in a wall thereof and through which a substrate may be transferred; a door movably coupled to the housing in a plane substantially parallel to the wall of the housing for selectively sealing the opening; a compressible sealing member disposed at least partly between an upper surface of the door and a corresponding surface of the housing for forming a seal therebetween by compression of the compressible sealing member in a direction substantially perpendicular to the wall when the door is in a closed position; and a mechanism for restricting the exposure of the compressible sealing member to an environment on a process chamber side of the housing.

US Patent:

7872495, Jan 18, 2011

Filed:

Jan 28, 2010

Appl. No.:

12/695992

Inventors:

Toan D. Tran - San Jose CA, US
Cheng H. Hsieh - Los Gatos CA, US
Mark J. Marlett - Livermore CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/003

US Classification:

326 30, 326 34

Abstract:

A unit cell for a programmable termination circuit in an integrated circuit and a method for programming such termination circuit are described. In an embodiment, such unit cells may have three n-type and three p-type transistors. A first transistor is coupled to receive a first float control signal. A second transistor is coupled to receive a second float control signal. The third and fourth transistors are coupled to receive a first termination voltage control signal. The fifth and sixth transistors are coupled to receive a second termination voltage control signal. The first float control signal and the second float control signal are a pair of complementary signals.

US Patent:

8217682, Jul 10, 2012

Filed:

Aug 10, 2010

Appl. No.:

12/854107

Inventors:

Greg W. Starr - San Jose CA, US
Toan D. Tran - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/094

US Classification:

326 86, 326 83

Abstract:

Embodiments of an integrated circuit driver, a method for operating integrated circuit driver, and predrivers are described. In one embodiment of the integrated circuit driver, a bias control circuit provides a bias signal for a first mode and a second mode. The bias signal has a first voltage level associated with operation in the first mode and a second voltage level associated with operation in the second mode. An output driver circuit receives the bias signal. In the first mode, the output driver circuit operates as a supply referenced driver, and in the second mode, the output driver circuit operates as a ground referenced driver.

US Patent:

8395446, Mar 12, 2013

Filed:

Jan 22, 2010

Appl. No.:

12/692105

Inventors:

Toan D. Tran - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03F 3/45

US Classification:

330254, 330261

Abstract:

Method and apparatus for amplification in an IC are described. A dual mode isolation amplifier having two modes of operation is provided. In the first mode of operation for a resistor-loaded differential transconductance with additional gain, a first switch circuit is placed in a substantially nonconductive state for electrically decoupling from a first current source node and a second current source node. A second switch circuit is placed in a substantially conductive state for electrically coupling a capacitor thereof to the first current source node and the second current source node. At high frequencies, a first resistance associated with the capacitor coupled in parallel with a resistive load is substantially reduced. The resistive load is coupled between the first current source node and the second current source node. The first resistance is reduced by approximating a short circuit by the capacitor during high-frequency operation.

US Patent:

20030027428, Feb 6, 2003

Filed:

Jul 18, 2001

Appl. No.:

09/908822

Inventors:

Wendy Ng - San Jose CA, US
Toan Tran - San Jose CA, US

Assignee:

Applied Materials, Inc.

International Classification:

H01L021/302
H01L021/461

US Classification:

438/706000

Abstract:

Accumulation of material in an endpoint detection cell downstream of a CVD chamber is avoided by selectively isolating the endpoint detection cell from chamber exhaust. During initial and midpoint phases of a plasma-based semiconductor fabrication process when concentration of materials in the chamber exhaust is heaviest, a bypass valve is closed and the endpoint detection cell is isolated from exposure to exhaust from the chamber. As endpoint of the plasma-based process approaches, the isolation valve is opened and the detection cell is exposed to chamber exhaust and can accurately detect the precise endpoint of the process. By selectively isolating the endpoint detector in accordance with embodiments of the present invention, unwanted accumulation of deposited materials that could degrade reliability of an optical or RF power endpoint detection signal is avoided.

US Patent:

20040089420, May 13, 2004

Filed:

Oct 30, 2003

Appl. No.:

10/699137

Inventors:

Wendy Ng - San Jose CA, US
Toan Tran - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23F001/00
H01L021/306

US Classification:

156/345100

Abstract:

Accumulation of material in an endpoint detection cell downstream of a CVD chamber is avoided by selectively isolating the endpoint detection cell from chamber exhaust. During initial and midpoint phases of a plasma-based semiconductor fabrication process when concentration of materials in the chamber exhaust is heaviest, a bypass valve is closed and the endpoint detection cell is isolated from exposure to exhaust from the chamber. As endpoint of the plasma-based process approaches, the isolation valve is opened and the detection cell is exposed to chamber exhaust and can accurately detect the precise endpoint of the process. By selectively isolating the endpoint detector in accordance with embodiments of the present invention, unwanted accumulation of deposited materials that could degrade reliability of an optical or RF power endpoint detection signal is avoided.

US Patent:

20040163590, Aug 26, 2004

Filed:

Feb 24, 2003

Appl. No.:

10/374571

Inventors:

Toan Tran - San Jose CA, US
Steve Ghanayem - Los Altos CA, US
Sean Herbert - San Carlos CA, US
Won Bang - Santa Clara CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C016/00

US Classification:

118/715000

Abstract:

Early detection of clogging of a liquid precursor injection valve in a gas delivery system of a semiconductor fabrication tool is allowed through monitoring pressure upstream of the injection valve. The increase in pressure associated with obstruction of the valve may trigger an alarm alerting the operator, allowing for rapid correction of the problem before substantial numbers of wafers are improperly processed utilizing the clogged valve.