Todd A Morneau

age ~45

from Lincoln, MA

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Todd Morneau Phones & Addresses

213 Sandy Pond Rd, Lincoln, MA 01773 • (617)6458784
Sudbury, MA
Boston, MA
Troy, NY
Sunapee, NH

Work

Company:

Tenable
Jul 2019
Position:

Product management

Industries

Information Technology And Services

Resumes

Product Management

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Location:

Sudbury, MA

Industry:

Information Technology And Services

Work:

Tenable
Product Management
Threat Stack, Inc
Director, Product Management
Rsa Security
Rsa Labs 2.0
Rsa the Security Division of Emc
Principal Technologist, Office of the Chief Technology Officer
Rsa Security
Principal Technologist and Manager of Hardware Advanced Development

Us Patents

Indicating Errors In Connection With Devices
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US Patent:

8564453, Oct 22, 2013
Filed:

Sep 7, 2011
Appl. No.:

13/226878
Inventors:

Todd Morneau - Sudbury MA, US
Jon Busenkell - Hollis NH, US
Assignee:

EMC Corporation - Hopkinton MA
International Classification:

G08B 5/00
H04Q 1/30
G05B 19/00
US Classification:

3408154, 340 744, 340 532
Abstract:

A method and system for use in indicating errors in connection with devices, wherein at least one of the devices comprises a display is disclosed. An error indicator suitable for indicating an error in connection with the device is stored. The error indicator is mapped to a potential error in connection with the device. An error is detected in connection with the device. The error in connection with the device is determined in response to detecting the error. Based on determining the error, the error indicator is displayed on the display for enabling determination of the error in connection with the device.

Providing Security To An Electronic Device
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US Patent:

8452989, May 28, 2013
Filed:

Dec 9, 2009
Appl. No.:

12/634116
Inventors:

Todd Morneau - Sudbury MA, US
William Duane - Westford MA, US
Assignee:

EMC Corporation - Hopkinton MA
International Classification:

G06F 21/00
US Classification:

713193, 361764, 361767, 361782, 361783, 361784, 257678, 257686, 257777, 365 63
Abstract:

A technique provides security to an electronic device. The technique involves disposing a microprocessor between a printed circuit board and a circuit element to restrict physical access to the microprocessor, the microprocessor having (i) a bottom which faces the printed circuit board in a first direction and (ii) a top which faces the circuit element in a second direction which is opposite the first direction. The technique further involves delivering power to the microprocessor from a power source while the microprocessor is disposed between the printed circuit board and the circuit element, the microprocessor performing electronic operations in response to the power delivered from the power source. The technique further involves electronically altering or preventing the microprocessor from further performing the electronic operations in response to tampering activity on the circuit element. Such detection of the tampering activity may involve monitoring a covert signal for tamper evidence detection.