Tom Y Chang

US Patent:

7219275, May 15, 2007

Filed:

Feb 8, 2005

Appl. No.:

11/053631

Inventors:

Tom Y. Chang - Fishkill NY, US
William V. Huott - Holmes NY, US
Thomas J. Knips - Wappingers Falls NY, US
Donald W. Plass - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/00
G01R 31/28

US Classification:

714718, 714733

Abstract:

A method and apparatus for providing flexible modular redundancy allocation for memory built in self test of random access memory with redundancy. The apparatus includes a first redundancy support register that includes inputs for receiving an address of a location in memory under test and data relating to must fix repair elements. The address includes a row and column vector of the location. The first redundancy support register also includes outputs for transmitting the address and data. The apparatus also includes a second redundancy support register including inputs for receiving the address and data from the outputs of the first redundancy support register. Each of the inputs of the second redundancy support register shares a one-to-one correspondence to each of the outputs of the first redundancy support register. The apparatus further includes allocation logic for providing a modular implementation of the first redundancy support register and the second redundancy support register.

US Patent:

7437626, Oct 14, 2008

Filed:

Feb 11, 2005

Appl. No.:

11/056726

Inventors:

Tom Y. Chang - Fishkill NY, US
William V. Huott - Holmes NY, US
Thomas J. Knips - Wappinger Falls NY, US
Donald W. Plass - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/00

US Classification:

714710, 714733, 714734

Abstract:

Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.

US Patent:

7793173, Sep 7, 2010

Filed:

Jun 30, 2008

Appl. No.:

12/164869

Inventors:

Tom Y. Chang - Fishkill NY, US
William V. Huott - Holmes NY, US
Thomas J. Knips - Wappinger Falls NY, US
Donald W. Plass - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/00

US Classification:

714710, 714733

Abstract:

Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.

US Patent:

20040205435, Oct 14, 2004

Filed:

Apr 14, 2003

Appl. No.:

10/413613

Inventors:

Thomas Knips - Wappingers Falls NY, US
Tom Chang - Poughkeepsie NY, US
James Dawson - Poughkeepsie NY, US
Douglas Malone - Pleasant Valley NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R031/28

US Classification:

714/733000

Abstract:

Method and system for testing a memory array having a non-uniform binary address space. The test system includes a test engine for generating addresses for the memory array and for generating and applying data patterns to the memory array. The test engine has an address generator including a series combination of a linear register and a binary counter for generating the non-uniform address.