Tony H Cheng

US Patent:

8006062, Aug 23, 2011

Filed:

May 9, 2008

Appl. No.:

12/118176

Inventors:

Tony Yuhsiang Cheng - Union City CA, US
Hon Fei Chong - Campbell CA, US
Benjamin Dodge - San Jose CA, US
Howard Tsai - Cupertino CA, US
Tsungyi Lin - Santa Clara CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711170, 711104, 711156, 711E12001, 713 1

Abstract:

A computing system has a mode of operation in which at least two different memory parameter profiles are read by a BIOS to configure memory. In one implementation the memory parameter profiles are stored in a serial presence detect memory using an extended serial presence detect format.

US Patent:

20140032947, Jan 30, 2014

Filed:

Jul 30, 2012

Appl. No.:

13/561884

Inventors:

Sagheer Ahmad - Cupertino CA, US
Edward L. Riegelsberger - Fremont CA, US
Tony Yuhsiang Cheng - Union City CA, US
Laurent Rene Moll - San Jose CA, US
Brian Keith Langendorf - Benicia CA, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06F 1/00

US Classification:

713320, 713300

Abstract:

A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.

US Patent:

20210042417, Feb 11, 2021

Filed:

Oct 27, 2020

Appl. No.:

17/081722

Inventors:

- Santa Clara CA, US
Ryan Speiser - Santa Clara CA, US
Varun Kumar - Santa Clara CA, US
Tony Cheng - Santa Clara CA, US
Erik Zuroski - Saint Louis Park MN, US

International Classification:

G06F 21/57
H04L 9/32
G06F 21/74
G06F 21/76

Abstract:

A game cloud server, a method of operating a cloud server, and a method of playing a game on a game cloud server are disclosed. In one example, the game cloud server includes: (1) one or more processing units that virtually supports different gaming applications according to a gaming operating mode, and (2) an operating mode selector that is coupled to the one or more processing units and has (2A) a virtual fusing register that selects the gaming operating mode for executing the different virtually supported gaming applications, and (2B) a security processor that enables a secure virtual fusing based on documented security files authorizing selection of the gaming operating mode, separately from executing an operating system of the one or more processing units, wherein the gaming operating mode is a reconfigurable operating mode selectable from at least one signed license file of the documented security files.

US Patent:

20170091458, Mar 30, 2017

Filed:

Sep 30, 2015

Appl. No.:

14/870612

Inventors:

- Santa Clara CA, US
Ryan Speiser - Santa Clara CA, US
Varun Kumar - Santa Clara CA, US
Tony Cheng - Santa Clara CA, US
Erik Zuroski - Saint Louis Park MN, US

International Classification:

G06F 21/57
H04L 9/32

Abstract:

A secure reconfigurable operating mode system includes a hardware device having multiple operating modes and an operating mode selector that is coupled to the hardware device. The operating mode selector has a virtual fusing register that selects an operating mode for the hardware device and a security processor that enables a secure virtual fusing based on documented security files authorizing selection of the operating mode. A method of secure hardware device operating mode reconfiguration is also provided.

US Patent:

20140204540, Jul 24, 2014

Filed:

Jan 19, 2013

Appl. No.:

13/745747

Inventors:

- San Jose CA, US
Tony Chuen-Yiu CHENG - San Jose CA, US

Assignee:

SUPER MICRO COMPUTER INC. - San Jose CA

International Classification:

H05K 5/00

US Classification:

361732

Abstract:

A server for shortening development schedule is disclosed. A case has two tray receiving spaces. Each tray receiving space has a first opening and a second opening. Power sockets are disposed at the same position in the tray receiving spaces correspondingly. A storage unit includes a tray, a mother board and a storage component. The tray is inserted to the tray receiving space from the first opening and disposed extending to the opposite second opening. The storage unit is electrically connects with the power socket and fixed in the tray receiving space through a locking structure.

US Patent:

20140189180, Jul 3, 2014

Filed:

Dec 31, 2012

Appl. No.:

13/732060

Inventors:

- Santa Clara CA, US
Brian Keith Langendorf - Benicia CA, US
Sharath Raghava - Campbell CA, US
Tony Yuhsiang Cheng - Union City CA, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06F 13/372

US Classification:

710117

Abstract:

A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level.

US Patent:

20140181391, Jun 26, 2014

Filed:

Dec 26, 2012

Appl. No.:

13/726926

Inventors:

- Santa Clara CA, US
Tony Yuhsiang Cheng - Union City CA, US
Sharath Raghava - Campbell CA, US
Ambuj Kumar - Sunnyvale CA, US
Arunjit Sahni - San Jose CA, US
Paul Lam - Kitchener, CA

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G11C 11/56

US Classification:

711105

Abstract:

A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.

US Patent:

20140181392, Jun 26, 2014

Filed:

Dec 26, 2012

Appl. No.:

13/727078

Inventors:

- Santa Clara CA, US
Tony Yuhsiang Cheng - Union City CA, US
Sharath Raghava - Campbell CA, US
Ambuj Kumar - Sunnyvale CA, US
Arunjit Sahni - San Jose CA, US
Paul Lam - Kitchener, CA

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G11C 7/10

US Classification:

711105

Abstract:

A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.