Tony Y Cheng

US Patent:

8006062, Aug 23, 2011

Filed:

May 9, 2008

Appl. No.:

12/118176

Inventors:

Tony Yuhsiang Cheng - Union City CA, US
Hon Fei Chong - Campbell CA, US
Benjamin Dodge - San Jose CA, US
Howard Tsai - Cupertino CA, US
Tsungyi Lin - Santa Clara CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711170, 711104, 711156, 711E12001, 713 1

Abstract:

A computing system has a mode of operation in which at least two different memory parameter profiles are read by a BIOS to configure memory. In one implementation the memory parameter profiles are stored in a serial presence detect memory using an extended serial presence detect format.

US Patent:

20130236144, Sep 12, 2013

Filed:

Mar 6, 2013

Appl. No.:

13/786867

Inventors:

Tony Cheng - Laguna Niguel CA, US
Yumei Zhan - Kunshan, CN
Junxing Cao - Kunshan, CN

Assignee:

CELERITY TECHNOLOGIES INC. - Irvine CA

International Classification:

G02B 6/42
G02B 6/44

US Classification:

385 89, 385102

Abstract:

A connecting device for a fiber optic cable includes a first part having a first housing and first and second electrical connectors located on the first housing, and a second part having a second housing and a third electrical connector located on the second housing. The second and third electrical connectors are adapted to be mechanically and electrically connect with each other or disconnected from each other. The first part further includes electrical components disposed within the first housing and electrically connected to the first and second electrical connectors. The second part receives end portions of optical fibers of the fiber optic cable, and further includes optical transceivers disposed within the second housing which are electrically connected to the third electrical connector and optically coupled to the optical fibers. Also disclosed is a cable device employing an optical fiber cable and two connecting devices at its two ends, where at least one of the connecting devices has a structure described above.

US Patent:

20150338591, Nov 26, 2015

Filed:

Aug 6, 2015

Appl. No.:

14/820432

Inventors:

- Irvine CA, US
Tony Cheng - Laguna Niguel CA, US
Yumei Zhan - Kunshan, CN
Junxing Cao - Kunshan, CN

Assignee:

Celerity Technologies Inc. - Irvine CA

International Classification:

G02B 6/44

Abstract:

A fiber optic cable is disclosed, a fiber optic cable containing multiple optical fibers within an enclosure, where the fibers are divided into two groups, the first group of fibers being arrayed together and the second group being free fibers. The arrayed fibers are used to carry signals that are desired to be maintained in synchronization with each other, while the free fibers are used to carry signals whose synchronization with other signals is not important. In one example, four optical fibers form a linear array, and two free optical fibers are arranged on two sides of the linear array.

US Patent:

20140189180, Jul 3, 2014

Filed:

Dec 31, 2012

Appl. No.:

13/732060

Inventors:

- Santa Clara CA, US
Brian Keith Langendorf - Benicia CA, US
Sharath Raghava - Campbell CA, US
Tony Yuhsiang Cheng - Union City CA, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06F 13/372

US Classification:

710117

Abstract:

A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level.

US Patent:

20140181391, Jun 26, 2014

Filed:

Dec 26, 2012

Appl. No.:

13/726926

Inventors:

- Santa Clara CA, US
Tony Yuhsiang Cheng - Union City CA, US
Sharath Raghava - Campbell CA, US
Ambuj Kumar - Sunnyvale CA, US
Arunjit Sahni - San Jose CA, US
Paul Lam - Kitchener, CA

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G11C 11/56

US Classification:

711105

Abstract:

A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.

US Patent:

20140181392, Jun 26, 2014

Filed:

Dec 26, 2012

Appl. No.:

13/727078

Inventors:

- Santa Clara CA, US
Tony Yuhsiang Cheng - Union City CA, US
Sharath Raghava - Campbell CA, US
Ambuj Kumar - Sunnyvale CA, US
Arunjit Sahni - San Jose CA, US
Paul Lam - Kitchener, CA

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G11C 7/10

US Classification:

711105

Abstract:

A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.

US Patent:

20140181429, Jun 26, 2014

Filed:

Dec 26, 2012

Appl. No.:

13/727333

Inventors:

- Santa Clara CA, US
Tony Yuhsiang Cheng - Union City CA, US
Ambuj Kumar - Sunnyvale CA, US
Brian Keith Langendorf - Benicia CA, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711154

Abstract:

A method of training a memory interface between a memory controller and a memory module. The method includes programming a delay line of a data strobe with a delay value and programming a reference voltage with a voltage value. The method then writes a data bit pattern to the memory module wherein the data bit pattern is of a first plurality of unique data bit patterns. The data bit pattern is read back and a result is compared with the data bit pattern. A determination is made whether the memory module is in a pass state or an error state based on the comparing. The steps are repeated with another data bit pattern of the first plurality of data bit patterns. The method is repeated for each combination of the data strobe delay value and the reference voltage value.

US Patent:

20140181451, Jun 26, 2014

Filed:

Dec 27, 2012

Appl. No.:

13/728953

Inventors:

- Santa Clara CA, US
Tony Yuhsiang Cheng - Union City CA, US
Sharath Raghava - Campbell CA, US
Ambuj Kumar - Sunnyvale CA, US
Arunjit Sahni - San Jose CA, US
Paul Lam - Kitchener, CA

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711166, 711167

Abstract:

A method of training a command signal for a memory module. The method includes programming a memory controller into a mode wherein a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.