Tony San

US Patent:

6956512, Oct 18, 2005

Filed:

Jan 24, 2003

Appl. No.:

10/351076

Inventors:

Tony San - Sunnyvale CA, US
Jinyan Zhang - Santa Clara CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03M001/10
G01R027/02
G01R035/00
G06F019/00

US Classification:

341120, 324607, 702107

Abstract:

Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based implementation or a resistor-ladder-based implementation.

US Patent:

7089173, Aug 8, 2006

Filed:

Mar 30, 2001

Appl. No.:

09/823700

Inventors:

Philippe Molson - San Jose CA, US
Tony San - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 9/45

US Classification:

703 22, 705 4, 708491, 713200

Abstract:

Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, the present invention provides to an end customer IP hardware which is suitable for prototype testing, but unusable for production purposes. One method limits the physical or electrical mode of operation of a hardware platform used for prototype testing of intellectual property (such as limiting the number of electrical contacts between the hardware and an external electrical device or limiting the data format(s) usable in the hardware during prototype testing). Another method limits the temporal operation of a hardware platform using an internal counter within the software provided by the intellectual property owner. Once a clock count limit is reached, the software disables the hardware in one or more prescribed ways, such as a reset of one or more registers, a global tri-state of the hardware IO, or a random failure of some type.

US Patent:

7110927, Sep 19, 2006

Filed:

Jan 31, 2001

Appl. No.:

09/773853

Inventors:

Tony San - Sunnyvale CA, US
Philippe Molson - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50
G06F 7/60

US Classification:

703 13, 703 14

Abstract:

A method, apparatus and system for building a filter is disclosed. In a particular embodiment, the filter is a finite impulse response (FIR) filter and a compiler suitable for implementing the FIR filter is described. The compiler has a filter coefficient generator suitably arranged to provide a first set of filter coefficients corresponding to the desired FIR filter spectral response and a filter spectral response analyzer coupled to the filter coefficient generator for providing expected FIR filter spectral response based in part upon the first set of filter coefficients. The compiler also includes a filter resource estimator coupled to the filter spectral response simulator for estimating an implementation cost of the FIR filter based upon the second set of filter coefficients as well as a filter compiler unit coupled to the resource estimator arranged to compile a FIR filter implementation output file.

US Patent:

7119730, Oct 10, 2006

Filed:

Jul 25, 2005

Appl. No.:

11/189436

Inventors:

Tony San - Sunnyvale CA, US
Jinyan Zhang - Santa Clara CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03M 1/34
H03M 1/78
H03M 3/00

US Classification:

341163, 341143, 341154

Abstract:

Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based implementation or a resistor-ladder-based implementation.

US Patent:

7318014, Jan 8, 2008

Filed:

May 31, 2002

Appl. No.:

10/160142

Inventors:

Philippe Molson - San Jose CA, US
Tony San - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50
G06F 7/38

US Classification:

703 13, 703 14, 712224, 712225, 712226, 712227, 716 1, 716 7, 716 8

Abstract:

A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the system level simulator. These simulations take advantage of the computational capabilities of the simulation processor. To take advantage of the simulation processor's resources (e. g. , certain FPU components), the signals used in the simulation are made to conform to the native word type of the simulation processor. The hardware blocks deployed in a design frequently use non-native (from the simulation processor's perspective) word types. The bit accurate simulator casts words (signals) defined in the hardware design from a non-native format to a multi-bit native format suitable for use by the simulation processor. At various stages in the simulation, the simulator checks the “value” of the signal to determine whether that value is allowed by a word format specified by the hardware design.

US Patent:

7321327, Jan 22, 2008

Filed:

Sep 3, 2006

Appl. No.:

11/469862

Inventors:

Tony San - Sunnyvale CA, US
Jinyan Zhang - Santa Clara CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03M 1/66

US Classification:

341144, 341118

Abstract:

Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based implementation or a resistor-ladder-based implementation.

US Patent:

7480603, Jan 20, 2009

Filed:

Aug 16, 2006

Appl. No.:

11/505710

Inventors:

Tony San - Sunnyvale CA, US
Philippe Molson - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06G 7/02
G06G 7/62

US Classification:

703 13, 703 14, 708819

Abstract:

A method, apparatus and system for building a filter is disclosed. In a particular embodiment, the filter is a finite impulse response (FIR) filter and a compiler suitable for implementing the FIR filter is described. The compiler includes a filter coefficient generator suitably arranged to provide a first set of filter coefficients corresponding to the desired FIR filter spectral response and a filter spectral response analyzer coupled to the filter coefficient generator for providing an expected FIR filter spectral response based in part upon the first set of filter coefficients. The compiler also includes a filter resource estimator coupled to the filter spectral response simulator for estimating an implementation cost of the FIR filter based upon the second set of filter coefficients as well as a filter compiler unit coupled to the resource estimator arranged to compile a FIR filter implementation output file.

US Patent:

7509246, Mar 24, 2009

Filed:

Jun 9, 2003

Appl. No.:

10/458516

Inventors:

Philippe Molson - San Jose CA, US
Tony San - Sunnyvale CA, US
Jeffrey R. Fox - Los Gatos CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 13, 717135, 717140

Abstract:

Methods and apparatus automate creation of code for system level simulations from hardware representations, specifically RTL representations. In one approach, individual RTL hardware modules are analyzed to generate code for corresponding system level modules. This is accomplished by taking a mapped netlist for a register transfer level (RTL) representation of the hardware module and converting it to what can be termed a “system level netlist. ” This system level netlist contains “system level instances” corresponding to “hardware cells” of the mapped netlist. A mapped netlist includes hardware cells corresponding to programmed hardware units of a target hardware device. The method generates corresponding functional representations (code for system level simulation) from these hardware cells. This functional representation is referred to herein as a system level instance. System level instances are generated for each of the hardware cells in a given hardware module.