Trong Van Luong

US Patent:

7414436, Aug 19, 2008

Filed:

Oct 24, 2007

Appl. No.:

11/877898

Inventors:

Peter J. Klim - Austin TX, US
Jethro C. Law - Austin TX, US
Trong V. Luong - Austin TX, US
Abraham Mathews - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19/00

US Classification:

326 93, 326121

Abstract:

A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

US Patent:

7525393, Apr 28, 2009

Filed:

Apr 26, 2007

Appl. No.:

11/740612

Inventors:

Hung C. Ngo - Austin TX, US
Fadi H. Gebara - Austin TX, US
Jethro C. Law - Austin TX, US
Trong V. Luong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03L 7/00

US Classification:

331 25, 331 16

Abstract:

A digital frequency multiplier circuit is disclosed. The digital frequency multiplier circuit includes a digitally controlled oscillator (DCO), a phase detector and a control circuit. The DCO generates an internal feedback signal. The phase detector detects a phase difference between the internal feedback signal and an external reference clock signal. Coupled between the phase detector and the DCO, the control circuit adjusts the DCO to align the internal feedback signal with the external reference clock signal after a phase difference between the internal feedback signal and the external reference clock signal has been detected. The control circuit also locks a modulation frequency of the DCO and monitors the state of the digital frequency multiplier circuit in order to maintain the lock.

US Patent:

7557616, Jul 7, 2009

Filed:

Jul 14, 2008

Appl. No.:

12/172656

Inventors:

Peter J. Klim - Austin TX, US
Jethro C. Law - Austin TX, US
Trong V. Luong - Austin TX, US
Abraham Matthews - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19/00

US Classification:

326 93, 326 98, 326121

Abstract:

A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

US Patent:

7587020, Sep 8, 2009

Filed:

Apr 25, 2007

Appl. No.:

11/739756

Inventors:

Jethro C. Law - Austin TX, US
Trong V. Luong - Austin TX, US
Hung C. Ngo - Austin TX, US
Peter J. Klim - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 25/00
H03K 23/50

US Classification:

377 94, 377119, 377124

Abstract:

A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.

US Patent:

20080116938, May 22, 2008

Filed:

Nov 16, 2006

Appl. No.:

11/560440

Inventors:

Hung C. Ngo - Austin TX, US
Peter Juergen Klim - Austin TX, US
Jente B. Kuang - Austin TX, US
Jethro C. Law - Austin TX, US
Trong V. Luong - Austin TX, US
Abraham Mathews - Austin TX, US

International Classification:

H03K 19/096

US Classification:

326 95

Abstract:

A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The dynamic node is coupled to an output with an inverting logic circuit. A hybrid keeper circuit, coupled to the dynamic node, uses a parallel NFET and a first PFET to produce the same current as a larger PFET when operated with a high voltage power supply. The common node of the combination is coupled to the dynamic node by second PFET larger than the first PFET in one embodiment. At high voltage, the hybrid keeper provides a strong keeper current when potential noise is highest. The hybrid keeper current is automatically reduced at low voltage allowing performance to be maintained while keeping the effective noise immunity of the high voltage operation.

US Patent:

20080265957, Oct 30, 2008

Filed:

Apr 25, 2007

Appl. No.:

11/739760

Inventors:

Trong V. Luong - Austin TX, US
Hung C. Ngo - Austin TX, US
Jethro C. Law - Austin TX, US
Peter J. Klim - Austin TX, US

International Classification:

H03L 7/06

US Classification:

327156

Abstract:

A phase detector which provides a dynamic output signal and which automatically resets if a reference clock signal and a feedback clock signal align after an output pulse is generated. With the phase detector in accordance with the present invention, when there is a difference between the positive clock edges of the reference clock signal and the feedback clock signal, the phase detector generates output pulse. The output is used to correct the feedback clock signal. In the next cycle, if the feedback signal is corrected so that both the reference clock signal and feedback clock signal are aligned, then the output signals are reset to zero. The ability to reset advantageously prevents an unexpected correction that can occur in certain phase detector designs.

US Patent:

20090108875, Apr 30, 2009

Filed:

Jul 16, 2008

Appl. No.:

12/174543

Inventors:

Peter J. Klim - Austin TX, US
Jethro C. Law - Austin TX, US
Trong V. Luong - Greensboro NC, US
Abraham Mathews - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19/096
G06F 17/50
H03K 19/00

US Classification:

326 95, 326 93, 716 6

Abstract:

A design structure for a circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.