Trung Trong Tran

US Patent:

7327199, Feb 5, 2008

Filed:

Sep 23, 2005

Appl. No.:

11/233963

Inventors:

David Kwong - Fremont CA, US
Trung Tran - Sunnyvale CA, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G01R 35/00

US Classification:

331 44, 324523, 702106

Abstract:

According to one embodiment, a phase-locked loop (PLL) device includes test circuitry for entering/exiting a test mode upon receiving a particular pulse train at a reference clock input of the PLL. In addition, exemplary methods are provided herein for entering a test mode and detecting loop filter leakage within the PLL. The methods described herein are performed without the use of a dedicated test pin.

US Patent:

20120030647, Feb 2, 2012

Filed:

Jul 28, 2011

Appl. No.:

13/193366

Inventors:

Guoqiang Wang - Albany CA, US
Jeffrey N. Correll - Cedar Park TX, US
Sadia B. Malik - Austin TX, US
Hugo A. Andrade - El Cerrito CA, US
Newton G. Petersen - Austin TX, US
Rhishikesh Limaye - Berkeley CA, US
Trung N. Tran - Fremont CA, US
Jacob Kornerup - Austin TX, US
Kaushik Ravindran - Berkeley CA, US
Guang Yang - San Jose CA, US

International Classification:

G06F 9/44

US Classification:

717105

Abstract:

System and method for specifying and implementing programs. A graphical program is created in a graphical specification and constraint language that allows specification of a model of computation and explicit declaration of constraints in response to user input. The graphical program includes a specified model of computation, a plurality of interconnected functional blocks that visually indicate functionality of the graphical program in accordance with the specified model of computation, and specifications or constraints for the graphical program or at least one of the functional blocks in the graphical program. The specified model of computation and specifications or constraints are useable to analyze the graphical program or generate a program or simulation.

US Patent:

20180044918, Feb 15, 2018

Filed:

Oct 23, 2017

Appl. No.:

15/790079

Inventors:

Tai Dung Nguyen - Fremont CA, US
Trung Quoc Tran - Fremont CA, US

International Classification:

E04C 2/52
E04B 1/24
E04B 2/00
E04C 2/04
E04C 2/06

Abstract:

Building structures can be fabricated at an offsite, and then assembled at the construction site. The building structures can include beams and wall panels having metal attachments. The beams and wall panels can be assembled by coupling the metal attachments, for example, by welding.

US Patent:

20170286169, Oct 5, 2017

Filed:

Mar 27, 2017

Appl. No.:

15/470374

Inventors:

- Austin TX, US
Hugo A. Andrade - El Cerrito CA, US
Ankita Prasad - San Francisco CA, US
Arkadeb Ghosal - Vacaville CA, US
Trung N. Tran - Fremont CA, US
Rhishikesh Limaye - Berkeley CA, US
Patricia Derler - Richmond CA, US
Jacob Kornerup - Austin TX, US

International Classification:

G06F 9/50

Abstract:

A method for automatically mapping program functions to distributed heterogeneous platforms based on hardware attributes and specified constraints is disclosed. The method includes receiving a plurality of program functions and determining constraint information for each. The method further includes determining attributes of a plurality of hardware processing elements, wherein ones of the plurality of hardware processing elements have different attributes with respect to other ones of the hardware processing elements. The plurality of program functions may be automatically mapped for execution on at least a subset of the hardware processing elements, wherein the mapping is based on constraint information and the attributes.

US Patent:

20170286342, Oct 5, 2017

Filed:

Mar 28, 2017

Appl. No.:

15/471792

Inventors:

- Austin TX, US
Kaushik Ravindran - Berkeley CA, US
Hugo A. Andrade - El Cerrito CA, US
Ankita Prasad - San Francisco CA, US
Arkadeb Ghosal - Vacaville CA, US
Trung N. Tran - Fremont CA, US
Rhishikesh Limaye - Berkeley CA, US
Jacob Kornerup - Austin TX, US

International Classification:

G06F 13/366
G06F 13/40

Abstract:

A method for determining timing constraints in dataflow models is disclosed. The method includes receiving node information specifying a plurality of dataflow nodes, as well as coupling between various ones of the dataflow nodes. The method further comprising receiving timing information specifying timing constraints for at least some of the dataflow nodes. Based on the node information, the couplings between the nodes, and the timing information, a timeline dependency graph (TDG). The timeline dependency graph illustrates a timeline, mappings between nodes with side effects to firing times of those nodes on the timeline, and dependencies between nodes.

US Patent:

20160040424, Feb 11, 2016

Filed:

Aug 5, 2015

Appl. No.:

14/819419

Inventors:

Tai Dung Nguyen - Fremont CA, US
Trung Quoc Tran - Fremont CA, US

International Classification:

E04B 2/58
E04C 2/52
E04B 2/00
E04B 1/24
E04C 2/04

Abstract:

Building structures can be fabricated at an offsite, and then assembled at the construction site. The building structures can include beams and wall panels having metal attachments. The beams and wall panels can be assembled by coupling the metal attachments, for example, by welding.