Tsutomu Kiyohara from 2200 Agnew Rd APT 305, Santa Clara, CA 95054, age 53

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Location:

Santa Clara, CA

Industry:

Semiconductors

Work:

Applied Materials
Product Marketing and Management
Applied Materials Japan Sep 1996 - Sep 2000
Product Management

Education:

University of Toronto 1991 - 1995
BSc, Industrial Engineering Ashbury College

Skills:

Semiconductor Industry
Semiconductors
Product Management
Product Marketing
Cross Functional Team Leadership

Overall Defect Reduction For Pecvd Films
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US Patent:

20080050932, Feb 28, 2008
Filed:

Aug 23, 2006
Appl. No.:

11/508545
Inventors:

Annamalai Lakshmanan - Santa Clara CA, US
Vu NT Nguyen - Santa Clara CA, US
Sohyun Park - Santa Clara CA, US
Ganesh Balasubramanian - Sunnyvale CA, US
Steven Reiter - Santa Clara CA, US
Tsutomu Kiyohara - Campbell CA, US
Francimar Schmitt - Santa Clara CA, US
Bok Hoen Kim - San Jose CA, US
International Classification:

H01L 21/473
US Classification:

438786, 438788, 438789
Abstract:

The present invention generally provides an apparatus and method for reducing defects on films deposited on semiconductor substrates. One embodiment of the present invention provides a method for depositing a film on a substrate. The method comprises treating the substrate with a first plasma configured to reduce pre-existing defects on the substrate, and depositing a film comprising silicon and carbon on the substrate by applying a second plasma generated from at least one precursor and at least one reactant gas.

Enhancement In Uv Curing Efficiency Using Oxygen-Doped Purge For Ultra Low-K Dielectric Film
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US Patent:

20130344704, Dec 26, 2013
Filed:

May 29, 2013
Appl. No.:

13/904468
Inventors:

Scott A. HENDRICKSON - Brentwood CA, US
Sanjeev BALUJA - Campbell CA, US
Tsutomu KIYOHARA - Santa Clara CA, US
Juan Carlos ROCHA-ALVAREZ - San Carlos CA, US
Alexandros T. DEMOS - Fremont CA, US
Assignee:

Applied Materials, Inc. - Santa Clara CA
International Classification:

H01L 21/768
US Classification:

438778
Abstract:

Embodiments of the invention provide methods for curing an ultra low-k dielectric film within a UV processing chamber. In one embodiment, the method includes depositing an ultra low-k dielectric layer on a substrate in a deposition chamber, and subjecting the deposited ultra low-k dielectric layer to a UV curing processes in a UV processing chamber. The method includes stabilizing the UV processing chamber by flowing an oxygen gas and a purge gas into the UV processing chamber at a flow ratio of about 1:50000 to about 1:100. While flowing the oxygen-doped purge gas, the substrate is exposed to UV radiation to cure the deposited ultra low-k dielectric layer. The inventive oxygen-doped purge curing process provides an alternate pathway to build silicon-oxygen network of the ultra low-k dielectric material, thereby accelerating cross-linking efficiency without significantly affecting the film properties of the deposited ultra low-k dielectric material.

Pecvd Oxide-Nitride And Oxide-Silicon Stacks For 3D Memory Application
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US Patent:

8076250, Dec 13, 2011
Filed:

Oct 6, 2010
Appl. No.:

12/899401
Inventors:

Nagarajan Rajagopalan - Santa Clara CA, US
Xinhai Han - Fremont CA, US
Ji Ae Park - Santa Clara CA, US
Tsutomu Kiyohara - Campbell CA, US
Sohyun Park - Santa Clara CA, US
Bok Hoen Kim - San Jose CA, US
Assignee:

Applied Materials, Inc. - Santa Clara CA
International Classification:

H01L 21/31
US Classification:

438763, 438712, 438585, 438396, 438710, 257E21485, 257E21409, 257288, 257530, 427255, 427 39
Abstract:

A layer stack of different materials is deposited on a substrate in a single plasma enhanced chemical vapor deposition processing chamber while maintaining a vacuum. A substrate is placed in the processing chamber and a first processing gas is used to form a first layer of a first material on the substrate. A plasma purge and gas purge are performed before a second processing gas is used to form a second layer of a second material on the substrate. The plasma purge and gas purge are repeated and the additional layers of first and second materials are deposited on the layer stack.

Gate Stack Materials For Semiconductor Applications For Lithographic Overlay Improvement
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US Patent:

20160203971, Jul 14, 2016
Filed:

Oct 8, 2015
Appl. No.:

14/879043
Inventors:

- Santa Clara CA, US
Praket P. JHA - San Jose CA, US
Xinhai HAN - Fremont CA, US
Nagarajan RAJAGOPALAN - Santa Clara CA, US
Bok Hoen KIM - San Jose CA, US
Tsutomu KIYOHARA - Santa Clara CA, US
Subbalakshmi SREEKALA - Milpitas CA, US
International Classification:

H01L 21/02
H01L 27/115
Abstract:

Embodiments of the disclosure provide methods and system for manufacturing film layers with minimum lithographic overlay errors on a semiconductor substrate. In one embodiment, a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber, forming a plasma in the presence of the depositing gas mixture in the processing chamber, applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber, and rotating the substrate while depositing a film layer on the substrate.

Methods For Maintaining Clean Etch Rate And Reducing Particulate Contamination With Pecvd Of Amorphous Silicon Filims
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US Patent:

20140272184, Sep 18, 2014
Filed:

Feb 12, 2014
Appl. No.:

14/179019
Inventors:

- Santa Clara CA, US
Xinhai HAN - Fremont CA, US
Nagarajan RAJAGOPALAN - Santa Clara CA, US
Bok Hoen KIM - San Jose CA, US
Yoichi SUZUKI - Chiba-Ken, JP
Tsutomu KIYOHARA - Santa Clara CA, US
Assignee:

APPLIED MATERIALS, INC. - Santa Clara CA
International Classification:

C23C 16/44
US Classification:

427534
Abstract:

Methods for maintaining clean etch rate and reducing particulate contamination with PECVD of amorphous silicon films are provided. The method comprises cleaning a processing chamber with a plasma comprising a cleaning gas, exposing at least a portion of the interior surfaces and components of the processing chamber to an oxidation gas and a nitration gas in the presence of a plasma and depositing a bi-layer seasoning layer on the interior surfaces and components of the processing chamber.

Tsutomu Kiyohara