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I am a member of The Multiple Listing Service and Pacific West Association of Realtors and I am an eight year real estate professional in both residential and commercial real estate. I am dedicated to providing excellent service and unparalleled communication to my customers. I am a knowledgeable and experienced professional who deals with real estate transactions on a day-to-day basis in all areas of Orange, Los Angeles, Riverside, and San Bernardino Counties. I have established a work ethic of honesty, integrity and trust. I focus on making my clients' priorities as my own, and providing the best experience possible for each and every one of my clients by striving to fully understand my clients' wants and needs even before any contracts are signed. My energy and efforts are the results of my hard work and dedication to my practice and I take initiative to grow and diversify my skills in an ever-changing market by continuously staying abreast with the market conditions and keeping current with today's technology. Being a residential and commercial real estate professional over time has provided me with the skills, knowledge, experience and expertise that enable me to negotiate for my clients and close deals. I also work with other top professionals within the industry, such as escrow officers, title representatives and insurance companies. These other professionals are part of my team that I work with to ensure that my clients get the full benefits throughout the whole transaction. This has made me became a trusted member among my colleagues and a trusted member of the community. I have one clear mission in mind, and that is to provide exceptional service to my clients. This translates to hard work, commitment, compassion, attention to detail, closed transactions and a desire to go beyond the scope of my clients’ expectations.
Us Patents
Flipped Die Stacks With Multiple Rows Of Leadframe Interconnects
- San Jose CA, US Belgacem Haba - Saratoga CA, US Tu Tam Vu - San Jose CA, US Rajesh Katkar - San Jose CA, US
International Classification:
H01L 25/065 H01L 23/495
Abstract:
Stacked microelectronic packages comprise microelectronic elements each having a contact-bearing front surface and edge surfaces extending away therefrom, and a dielectric encapsulation region contacting an edge surface. The encapsulation defines first and second major surfaces of the package and a remote surface between the major surfaces. Package contacts at the remote surface include a first set of contacts at positions closer to the first major surface than a second set of contacts, which instead are at positions closer to the second major surface. The packages are configured such that major surfaces of each package can be oriented in a nonparallel direction with the major surface of a substrate, the package contacts electrically coupled to corresponding contacts at the substrate surface. The package stacking and orientation can provide increased packing density.
Fan-Out Wafer-Level Packaging Using Metal Foil Lamination
- San Jose CA, US Rajesh Katkar - San Jose CA, US Long Huynh - Santa Clara CA, US Laura Wills Mirkarimi - Sunol CA, US Bongsub Lee - Mountain View CA, US Gabriel Z. Guevara - San Jose CA, US Tu Tam Vu - San Jose CA, US Kyong-Mo Bang - Fremont CA, US Akash Agrawal - San Jose CA, US
Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.
Fan-Out Wafer-Level Packaging Using Metal Foil Lamination
- San Jose CA, US Rajesh Katkar - San Jose CA, US Long Huynh - Santa Clara CA, US Laura Wills Mirkarimi - Sunol CA, US Bongsub Lee - Mountain View CA, US Gabriel Z. Guevara - San Jose CA, US Tu Tam Vu - San Jose CA, US Kyong-Mo Bang - Fremont CA, US Akash Agrawal - San Jose CA, US
Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.
Wafer-Level Packaging Using Wire Bond Wires In Place Of A Redistribution Layer
- San Jose CA, US Tu Tam Vu - San Jose CA, US Bongsub Lee - Mountain View CA, US Kyong-Mo Bang - Fremont CA, US Xuan Li - Santa Clara CA, US Long Huynh - Santa Clara CA, US Gabriel Z. Guevara - San Jose CA, US Akash Agrawal - San Jose CA, US Willmar Subido - San Jose CA, US Laura Wills Mirkarimi - Sunol CA, US
An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.
Wafer-Level Packaging Using Wire Bond Wires In Place Of A Redistribution Layer
- San Jose CA, US Tu Tam VU - San Jose CA, US Bongsub LEE - Mountain View CA, US Kyong-Mo BANG - Fremont CA, US Xuan LI - Santa Clara CA, US Long HUYNH - Santa Clara CA, US Gabriel Z. GUEVARA - San Jose CA, US Akash AGRAWAL - San Jose CA, US Willmar SUBIDO - Garland TX, US Laura Wills MIRKARIMI - Sunol CA, US
An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.
Southland Industries
Bim Project Lead
Rosendin Electric Sep 2008 - Mar 2017
Bim Manager, Corporate
Rosendin Electric Mar 2006 - Aug 2008
Bim Detailer
Skills:
Construction Management Contractors Project Estimation Submittals Construction Autocad Contract Management Value Engineering Pre Construction Building Information Modeling Renovation Subcontracting Leadership In Energy and Environmental Design Change Orders Process Scheduler Bim Construction Safety
Xperi Corporation Nov 2013 - Dec 2017
Package and Mechanical Engineer
Broadcom Nov 2011 - Oct 2013
Principal Package Engineer
Idt - Integrated Device Technology, Inc. Jul 1990 - Nov 2010
Package Engineer Manager
Education:
University of Dayton
Skills:
Ic Semiconductors Semiconductor Industry Manufacturing Characterization Engineering Product Development Product Engineering
Te Connectivity
Senior Rf Technician
Anritsu Feb 2011 - Apr 2011
Microwave Technician
Itt 1989 - 2010
Senior Rf and Systems Test Technician
Planar Microwave 1987 - 1989
Lead Senior Microwave Technician
Trw Microwave 1985 - 1987
Engineering Technician
Education:
Lakeshore Technical College
Skills:
Testing Rf Systems Engineering Electronics Troubleshooting Receiver System Testing Diagnostic Testing Microwave System Testing Dod Test Equipment Iso Engineering Management Engineering
Zia Khan (1982-1986), Maria Shkodriani (1979-1983), Chris Siekerman (1983-1987), Tu Vu (1988-1992), Alvin Darden (1983-1986), Ebony Pampkin (1992-1996)