Tuan V Luong

US Patent:

53815432, Jan 10, 1995

Filed:

Mar 3, 1994

Appl. No.:

8/206563

Inventors:

James S. Blomgren - San Jose CA
Mark Semmelmeyer - Sunnyvale CA
Tuan Luong - San Jose CA
Gary Baum - San Jose CA

Assignee:

Chips and Technologies Inc. - San Jose CA

International Classification:

G06F 106

US Classification:

395550

Abstract:

The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i. e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i. e.

US Patent:

52768252, Jan 4, 1994

Filed:

Mar 12, 1991

Appl. No.:

7/667942

Inventors:

James S. Blomgren - San Jose CA
Tuan Luong - San Jose CA
Winnie Yu - San Jose CA

Assignee:

Chips & Technologies, Inc. - San Jose CA

International Classification:

G06F 938

US Classification:

395375

Abstract:

A method and apparatus for performing a fast jump address calculation is disclosed. A field from the instruction is provided to an adder, on the assumption that it is the displacement value, without actually determining whether it is a displacement value. A fixed instruction length is also provided to the adder, on the assumption that the instruction will have that length. Finally, the current instruction address bits from the program counter are provided to the adder. These are added together to provide a jump address.

US Patent:

53255160, Jun 28, 1994

Filed:

Mar 9, 1992

Appl. No.:

7/848544

Inventors:

James S. Blomgren - San Jose CA
Mark Semmelmeyer - Sunnyvale CA
Tuan Luong - San Jose CA
Gary Baum - San Jose CA

Assignee:

Chips and Technologies Inc. - San Jose CA

International Classification:

G06F 1300

US Classification:

395550

Abstract:

The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i. e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i. e.

US Patent:

53136063, May 17, 1994

Filed:

Jan 17, 1991

Appl. No.:

7/642977

Inventors:

Tuan Luong - San Jose CA
James S. Blomgren - San Jose CA
Winnie Yu - San Jose CA

Assignee:

Chips and Technologies, Inc. - San Jose CA

International Classification:

G06F 1214

US Classification:

395425

Abstract:

An improved system for checking for segmentation violations counts the total number of bytes accessed from the control segment following a control transfer operation. If the count indicates that a part of an instruction is fetched from outside the control segment a limit exception occurs.

US Patent:

61287032, Oct 3, 2000

Filed:

Sep 5, 1997

Appl. No.:

8/924113

Inventors:

Philip Bourekas - San Jose CA
Tuan Anh Luong - San Jose CA
Michael Miller - Saratoga CA

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

G06F 1208

US Classification:

711138

Abstract:

An apparatus and method for prefetching data into a cache memory system is provided. A prefetch instruction includes a hint type that allows a programmer to designate whether, during a data retrieval operation, a hit in the cache is to be ignored or accepted. If accepted, the prefetch operation completes. If ignored, the prefetch operation retrieves data from the main memory, even though the cache believes it contains valid data at the requested memory location. Use of this invention in a multiple bus master processing environment provides the advantages of using a cache memory, i. e. , burst reads and a relatively large storage space as compared to a register file, without incurring disadvantages associated with maintaining data coherency between the cache and main memory systems.