Tuan Q Pham

US Patent:

6337246, Jan 8, 2002

Filed:

Apr 2, 2001

Appl. No.:

09/824841

Inventors:

Daniel Sobek - Portola Valley CA
Timothy Thurgate - Sunnyvale CA
Carl R. Huster - San Jose CA
Tuan Duc Pham - Santa Clara CA
Mark T. Ramsbey - Sunnyvale CA
Sameer S. Haddad - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218247

US Classification:

438264

Abstract:

A method for making a ULSI MOSFET chip includes forming a MOSFET gate stack on a substrate, with a tunnel oxide layer being sandwiched between the gate stack and substrate. To prevent thickening of the tunnel oxide layer into a âgate edge liftingâ profile during subsequent oxidation-causing steps, at least one protective barrier film is deposited or grown over the gate stack and tunnel oxide layer immediately after gate stack formation. Then, subsequent steps, including forming source and drain regions for the gate stack, can be undertaken without causing thickening of the tunnel oxide layer.

US Patent:

6342415, Jan 29, 2002

Filed:

Sep 23, 1999

Appl. No.:

09/404395

Inventors:

Angela T. Hui - Fremont CA
Tuan Duc Pham - Santa Clara CA
Mark T. Ramsbey - Sunnyvale CA
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218238

US Classification:

438212, 438213, 438270, 438210, 257308

Abstract:

A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The at least one contact has a reduced width that is less than approximately 0. 28 microns.

US Patent:

6355514, Mar 12, 2002

Filed:

Jun 19, 2000

Appl. No.:

09/597358

Inventors:

Tuan Pham - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218247

US Classification:

438211, 257315, 257314

Abstract:

The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual ONO floating gates with an isolation spacer between floating gates. Processes for making the memory device according to the invention are also provided.

US Patent:

6369416, Apr 9, 2002

Filed:

Sep 23, 1999

Appl. No.:

09/404394

Inventors:

Angela T. Hui - Fremont CA
Tuan Duc Pham - Santa Clara CA
Mark T. Ramsbey - Sunnyvale CA
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976

US Classification:

257288, 257296, 257306, 257315, 257368, 257390

Abstract:

A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The contact has a side defining a sloped profile. The sloped profile includes an angle between the side of the contact and a surface of the substrate that is less than approximately eighty-eight degrees.

US Patent:

6399984, Jun 4, 2002

Filed:

Jun 15, 2001

Appl. No.:

09/882242

Inventors:

Yider Wu - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Chi Chang - Redwood City CA
Yu Sun - Saratoga CA
Tuan Duc Pham - Santa Clara CA
Jean Y. Yang - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257316, 257314

Abstract:

A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.

US Patent:

6448608, Sep 10, 2002

Filed:

Aug 4, 2000

Appl. No.:

09/631894

Inventors:

Tuan Duc Pham - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Sameer S. Haddad - San Jose CA
Angela T. Hui - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257316, 257314, 257315, 438258

Abstract:

An improved flash memory device, which comprises core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer, and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The use of a high energy dopant implant to pass through dopant through the insulating layer, the protective layer, and the oxide layer into the substrate without the use of a self aligned source etch, reduces damage to the core stacks and periphery stacks caused by various etches during the production of the flash memory device and provides insulation to reduce unwanted current leakage between the tungsten plug and the stacks.

US Patent:

6455373, Sep 24, 2002

Filed:

Apr 12, 2001

Appl. No.:

09/834419

Inventors:

Tuan D. Pham - Santa Clara CA
Mark T. Ramsbey - Sunnyvale CA
Sameer S. Haddad - San Jose CA
Angela T. Hui - Fremont CA
Yu Sun - Saratoga CA
Chi Chang - Redwood City CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438257, 438265

Abstract:

A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).

US Patent:

6465303, Oct 15, 2002

Filed:

Jun 20, 2001

Appl. No.:

09/885490

Inventors:

Mark T. Ramsbey - Sunnyvale CA
Narbeh Derhacobian - Belmont CA
Janet Wang - San Francisco CA
Angela Hui - Fremont CA
Tuan Pham - Santa Clara CA
Ravi Sunkavalli - Milpitas CA
Mark Randolph - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438257, 438231

Abstract:

One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.