Tuan Hong Phan

US Patent:

6367042, Apr 2, 2002

Filed:

Dec 11, 1998

Appl. No.:

09/209996

Inventors:

Tuan L. Phan - San Jose CA
V. Swamy Irrinki - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3128

US Classification:

714733

Abstract:

A method for improving the fault coverage of manufacturing tests for integrated circuits having structures such as embedded memories. In the disclosed embodiment of the invention, the integrated circuit die of a semiconductor wafer are provided with a fuse array or other circuitry capable of storing an identification number. The integrated circuit die also include an embedded memory or similar circuit and built-in self-test (BIST) and built-in self-test (BISR) circuitry. At a point early in the manufacturing test process, the fuse array of each integrated circuit die is encoded with an identification number to differentiate the die from other die of the wafer or wafer lot. The integrity of the embedded memory of each integrated circuit die is then tested at the wafer level under a variety of operating conditions via the BIST and BISR circuitry. The results of these tests are stored in ATE and associated with a particular integrated circuit die via the identification number of the die. The manufacturing test process then continues for the packaged integrated circuits.

US Patent:

6425103, Jul 23, 2002

Filed:

Sep 29, 1999

Appl. No.:

09/407412

Inventors:

Tuan Phan - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3128

US Classification:

714733, 714738, 365221, 36523006, 36523008, 365236, 365239

Abstract:

A low-complexity method and apparatus for generating address sequences for the moving inversion test method. In one embodiment, the address sequence generator includes a ring of counter cells in which each cell is configured to provide a toggle signal to a subsequent cell. Each cell receives a distinct least significant bit selector signal which, when asserted, designates the subsequent cell as the least significant bit. When the least significant selector signal is asserted, the cell continuously asserts the toggle signal to the subsequent cell. When the selector signal is de-asserted, the cell asserts the toggle signal to the subsequent cell half as often as the toggle signal from the preceding cell. Each cell provides an output address bit which is toggled whenever the toggle signal from the preceding bit is asserted across a transition in a clock signal. This configuration causes the ring of cells to implement a counter with a selectable least significant bit.

US Patent:

6505313, Jan 7, 2003

Filed:

Dec 17, 1999

Appl. No.:

09/466389

Inventors:

Tuan Phan - San Jose CA
William Schwarz - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 2900

US Classification:

714718, 714733

Abstract:

A memory device configured to detect changes in fault patterns is disclosed. In one embodiment, the memory device includes a memory array, a built-in self-test (BIST) unit, and a built-in self-repair (BISR) unit. The BIST unit runs test patterns on the memory array to identify faulty locations in the array. A comparator within the BIST or external to the BIST compares the actual output of the memory array to the expected output, and asserts an error signal whenever a mismatch occurs. The BISR unit intercepts addresses directed to the memory array, and operates on the addresses in three distinct phases. During a training phase, the BISR unit stores the intercepted addresses when the error signal is asserted. During the normal operation phase, the BISR unit compares all intercepted addresses to stored addresses and redirects a corresponding memory access if any intercepted address matches a stored address. During a verification phase, the BISR unit compares intercepted addresses designated by assertions of the error signal to the addresses previously stored in the training phase.

US Patent:

6634003, Oct 14, 2003

Filed:

Feb 10, 2000

Appl. No.:

09/501807

Inventors:

Tuan Phan - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 2900

US Classification:

714710, 714798, 714733, 324537, 365 45, 365200, 365222

Abstract:

A system for disabling defective memory elements includes a memory array, an address decoder and a decoder element. The memory array has multiple memory elements for storing data. The address decoder receives a requested memory address and produces multiple element-select signals. Each element-select signal is associated with one of the memory elements and indicates whether access to the associated memory element is requested by the host. The decoder element receives one of the element-select signals and provides an output signal to the associated memory element. If the associated memory element is functional, the output signal enables or disables the associated memory element in accordance with the associated element-select signal. If, on the other hand, the associated memory element is defective, the output signal disables the associated memory element regardless of the associated element-select signal. The decoder element is programmed upon power-up so as not to require an address comparison for each memory access cycle.

US Patent:

6651202, Nov 18, 2003

Filed:

Mar 8, 2001

Appl. No.:

09/802198

Inventors:

Tuan L. Phan - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3128

US Classification:

714733, 714735

Abstract:

An integrated circuit includes built-in self test (BIST) and built-in self repair (BISR) circuitry, a fuse array capable of storing information related to defective memory locations identified during the manufacturing process. During manufacture, the integrity of the embedded memory of the integrated circuit is tested under a variety of operating conditions via the BIST/BISR circuitry. The repair solutions derived from these tests are stored and compiled in automated test equipment. If the repair solutions indicate that the embedded memory is repairable, the on-chip fuse array of the integrated circuit is programmed with information indicative of all of the detected defective memory locations. The built-in self repair circuitry of the integrated circuit is not executed upon power up. Instead, the repair information stored in the fuse array is provided to address remap circuitry within the BISR circuit.

US Patent:

6671842, Dec 30, 2003

Filed:

Oct 21, 1999

Appl. No.:

09/420636

Inventors:

Tuan Phan - Santa Clara CA
Thompson W. Crosby - San Jose CA
V. Swamy Irrinki - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3128

US Classification:

714733, 714744

Abstract:

A method and apparatus are disclosed for asynchronous testing of multiport memories. In one embodiment, the apparatus includes a built-in self-test (BIST) unit coupled to a multiport memory module and configured to apply a pattern of read and write test operations concurrently to multiple ports of the memory. The pattern of test operations may be any standard or customized pattern designed to establish the functionality of the multiport memory. The test operations to different ports are clocked by different clock signals so that the clock signals may be offset relative to each other by an adjustable or preset clock skew. Certain clock skews cause transitions to occur on signal lines in the memory array at the most sensitive portion(s) of a read cycle. The timing of these transitions, in combination with the presence of high-resistivity bridge faults, sufficiently disturbs the read cycle so as to cause a read error, thereby enabling detection of the bridge faults.

US Patent:

7536611, May 19, 2009

Filed:

Nov 3, 2003

Appl. No.:

10/700177

Inventors:

Mukesh K. Puri - Fremont CA, US
Ghasi R. Agrawal - Sunnyvale CA, US
Tuan L. Phan - San Jose CA, US

Assignee:

LST Corporation - Milpitas CA

International Classification:

G11C 29/00

US Classification:

714710

Abstract:

A BISR scheme which provides for on-chip assessment of the amount of repair on a given memory and for the flagging of any device as a fail when the device exceeds a pre-determined limit. Preferably, a counter is built and loaded through a test pattern during production testing, and the counter establishes the threshold for pass/fail criteria. The BISR is configured to load a repair solution and then test the memories for any additional failures and if there are any, repair them (provided enough redundant elements are available). In addition, a reliability controller for BISR designs can be provided, where the reliability controller contains a register set and a number of counters at the chip-level which can be loaded through a test pattern during production tests, where one of the counters contains the number of memories to be allowed for repair.

US Patent:

62276379, May 8, 2001

Filed:

May 14, 1998

Appl. No.:

9/078746

Inventors:

Tuan Phan - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01H 3776

US Classification:

325525

Abstract:

An information circuit in a semiconductor device suitable for encoding and retrieving a bit of information. The information circuit includes an input circuit and an output circuit. The input circuit includes an input node coupled to an input terminal of a transistor. The output circuit includes a load device, a fuse circuit, and first and second output terminals of the transistor all coupled in series between a power supply terminal and a ground terminal. The impedance of said fuse circuit is preferably alterable between an initial impedance and an altered impedance. An output node of said information circuit is coupled to said output circuit. The information circuit is configured such that the output node voltage is indicative of said impedance of said fuse circuit when said input node is biased to a "read" state, said power supply terminal is biased to a power supply voltage, and said ground terminal is grounded.