Tyler Crystal V Leuten

US Patent:

20200118941, Apr 16, 2020

Filed:

Oct 15, 2018

Appl. No.:

16/160222

Inventors:

- Santa Clara CA, US
Tyler LEUTEN - Orangevale CA, US
Maria Angela Damille RAMISO - Folsom CA, US

International Classification:

H01L 23/00
H01L 23/498
H01L 21/683
H01L 21/48

Abstract:

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of buildup layers, and where each buildup layer has fiber reinforcement. In an embodiment, the electronic package further comprises a reinforcement layer, where the reinforcement layer comprises a buildup layer and fiber reinforcement, and where an orientation of the fibers in the reinforcement layer is different than an orientation of the fibers in the package substrate.

US Patent:

20200120800, Apr 16, 2020

Filed:

Oct 11, 2018

Appl. No.:

16/157187

Inventors:

- Santa Clara CA, US
Tyler LEUTEN - Orangevale CA, US
Maria Angela Damille RAMISO - Folsom CA, US

International Classification:

H05K 1/14
H05K 1/11
H05K 1/18
H01R 12/52
H05K 3/00
H05K 3/34
H05K 3/36
H05K 3/28

Abstract:

Embodiments disclosed herein include modular electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first connector module having a notch on a first end and a plurality of surface mount technology (SMT) pads on a second end. In an embodiment, the electronics package further comprises a second connector module having a keyed connector on a first end and a plurality of SMT pads on a second end. In an embodiment, the electronics package further comprises a system in package (SIP) module between the first connector and the second connector, the component module electrically and mechanically coupled to the SMT pads of the first connector and the SMT pads of the second connector.

US Patent:

20200120808, Apr 16, 2020

Filed:

Oct 11, 2018

Appl. No.:

16/157185

Inventors:

- Santa Clara CA, US
Tyler LEUTEN - Orangevale CA, US

International Classification:

H05K 3/00
H05K 1/18
H05K 1/11

Abstract:

Embodiments disclosed herein include a printed circuit board (PCB) with a non-uniform thickness and methods of fabricating such PCBs. In an embodiment, the PCB comprises a connector region with a top surface and a bottom surface, and a component region with a top surface and a bottom surface. In an embodiment, the bottom surface of the connector region is coplanar with the bottom surface of the component region. In an embodiment the top surface of the connector region is not coplanar with the top surface of the component region.

US Patent:

20200051903, Feb 13, 2020

Filed:

Oct 21, 2019

Appl. No.:

16/658611

Inventors:

- Santa Clara CA, US
Tyler Leuten - Orangevale CA, US
Florence R. Pon - Folsom CA, US

International Classification:

H01L 23/498
H01L 23/538
H01L 23/522
H01L 25/065

Abstract:

Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.

US Patent:

20190312005, Oct 10, 2019

Filed:

Dec 31, 2016

Appl. No.:

16/468264

Inventors:

- Santa Clara CA, US
Tyler Leuten - Orangevale CA, US
John K. Yap - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/00
H01L 23/50
H01L 23/528
H01L 25/065

Abstract:

Electronic device package technology is disclosed. In one example, an electronic device comprises a die () having a bond pad (); and a decoupling capacitor () mounted on the die () and electrically coupled to the die (). A method for making an electronic device comprises mounting a decoupling capacitor () on a die (); and electrically coupling the decoupling capacitor () to the die ().

US Patent:

20190304886, Oct 3, 2019

Filed:

Apr 2, 2018

Appl. No.:

15/943391

Inventors:

- Santa Calara CA, US
Tyler Leuten - Orangevale CA, US

Assignee:

Intel Corporation - Santa Clalra CA

International Classification:

H01L 23/498
H05K 1/11
H01L 23/00

Abstract:

Embodiments include a microelectronic package structure having a substrate with one or more substrate pads on a first side of the package substrate. A ball interconnect structure is on the substrate pad, the ball interconnect structure comprising at least 99.0 percent gold. A discrete component having two or more component terminals is on the ball interconnect structure.

US Patent:

20180315699, Nov 1, 2018

Filed:

Jul 9, 2018

Appl. No.:

16/030053

Inventors:

- Santa Clara CA, US
Tyler Leuten - Orangevale CA, US
Florence R. Pon - Folsom CA, US

International Classification:

H01L 23/498
H01L 21/48
H01L 25/065
H01L 23/522

Abstract:

Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.

US Patent:

20180204821, Jul 19, 2018

Filed:

Sep 23, 2015

Appl. No.:

15/755219

Inventors:

- Santa Clara CA, US
Min-Tih Lai - Orangevale CA, US
Tyler Charles Leuten - Orangevale CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 25/065
H01L 23/538
H01L 23/00
H01L 23/498
H01L 21/48
H01L 25/00

Abstract:

Substrates, assemblies, and techniques for enabling multi-chip flip chip packages are disclosed herein. For example, in some embodiments, a package substrate may include a first side face; a second side face, wherein the second side face is opposite to the first side face along an axis; a portion of insulating material extending from the first side face to the second side face; wherein a cross-section of the portion of insulating material taken perpendicular to the axis has a stairstep profile. Solder pads may be disposed at base and step surfaces of the portion of insulating material. One or more dies may be coupled to the package substrate (e.g., to form a multi-chip flip chip package), and in some embodiments, additional IC packages may be coupled to the package substrate. In some embodiments, the package substrate may be reciprocally symmetric or approximately reciprocally symmetric.