Van Q Le

US Patent:

20190050049, Feb 14, 2019

Filed:

Sep 28, 2018

Appl. No.:

16/146454

Inventors:

- Santa Clara CA, US
Nageen Himayat - Fremont CA, US
Chaitanya Sreerama - Hillsboro OR, US
Hassnaa Moustafa - Portland OR, US
Rita Wouhaybi - Portland OR, US
Linda Hurd - Cool CA, US
Nadine L Dabby - Palo Alto CA, US
Van Le - Beaverton OR, US
Gayathri Jeganmohan - Folsom CA, US
Ankitha Chandran - Portland OR, US

International Classification:

G06F 1/32
G06N 5/04
G06N 99/00
G06K 9/00
G06T 15/00

Abstract:

Methods and apparatus to manage operation of variable-state computing devices using artificial intelligence are disclosed. An example computing device includes a hardware platform. The example computing device also includes an artificial intelligence (AI) engine to: determine a context of the device; and adjust an operation of the hardware platform based on an expected change in the context of the device. The adjustment modifies at least one of a computational efficiency of the device, a power efficiency of the device, or a memory response time of the device.

US Patent:

20190051642, Feb 14, 2019

Filed:

Sep 28, 2018

Appl. No.:

16/146445

Inventors:

- Santa Clara CA, US
Nageen Himayat - Fremont CA, US
Linda Hurd - Cool CA, US
Min Suet Lim - Gelugor, MY
Van Le - Beaverton OR, US
Gayathri Jeganmohan - Folsom CA, US
Ankitha Chandran - Portland OR, US

International Classification:

H01L 25/18
H01L 23/538
H01L 23/367
G06F 1/32
G06N 3/063
G06N 3/04
G06N 3/08

Abstract:

Methods and apparatus to implement efficient memory storage in multi-die packages are disclosed. An example multi-die package includes a multi-die stack including a first die and a second die. The second die is stacked on the first die. The multi-die package further includes a third die adjacent the multi-die stack. The multi-die package also includes a silicon-based connector to communicatively couple the multi-die stack and the third die. The silicon-based connector includes at least one of a logic circuit or a memory circuit.

US Patent:

20180374928, Dec 27, 2018

Filed:

Dec 24, 2015

Appl. No.:

15/776752

Inventors:

- Santa Clara CA, US
ASHISH AGRAWAL - Santa Clara CA, US
BENJAMIN CHU-KUNG - Portland OR, US
VAN H. LE - Portland OR, US
MATTHEW V. METZ - Portland OR, US
WILLY RACHMADY - Beaverton OR, US
JACK T. KAVALIEROS - Portland OR, US
RAFAEL RIOS - Austin TX, US

International Classification:

H01L 29/51
H01L 29/78
H01L 29/66
H01L 29/16

Abstract:

Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed.