Van Khanh Le

Address:

11210 Conchos Trl, Austin, TX 78726

Phone:

(512)2196884

VIN:

1GKFC16J17J262383

Make:

GMC

Model:

YUKON XL

Year:

2007

US Patent:

54756189, Dec 12, 1995

Filed:

Jan 28, 1993

Appl. No.:

8/014014

Inventors:

Van Le - Austin TX

Assignee:

Advanced Micro Devices - Sunnyvale CA

International Classification:

G01B 1500

US Classification:

364550

Abstract:

An improved ion implant device is provided having programmable and graphical user interface. The ion implant device can be accessed by a remote computer such as an IBM. RTM. -compatible PC/XT/AT personal computer to allow an operator to access, control and monitor the implant device from a remote location. Various control signals associated with implant operation can be changed or modified according to implant parameters stored within the computer. Each time a wafer lot is to be processed, the implant parameters can be quickly retrieved from the computer and read to the implant device with minimum operator error. Likewise, various implant parameters and/or implanter settings can be written to the computer and stored within the computer's memory. The computer can be easily interfaced or retrofitted to existing implant devices with only a minimum amount of necessary software code and associated hardware.

US Patent:

55837999, Dec 10, 1996

Filed:

Jan 18, 1994

Appl. No.:

8/182770

Inventors:

Van Le - Austin TX
Donald L. Friede - Austin TX

Assignee:

Advanced Micro Devices - Sunnyvale CA

International Classification:

G01B 2100

US Classification:

364563

Abstract:

A system for measuring thicknesses of a layered workpiece in a silicon integrated circuit manufacturing process. The system includes means for measuring a resistivity of said workpiece, such as an M-Gage; means for transforming a first signal set output by said means for measuring to a second signal set; and means for determining thicknesses of said workpiece layers from said resistivity capable of interpreting the second signal set. The means for transforming includes an interface board. The interface board receives the first signal set and emits the second signal set for receipt by the means for determining when an appropriate signal is received from the means for determining. [The interface board includes four inputs, first resistors connecting each of the inputs, transistors, each having a base, a collector, and an emitter, connecting each of the first resistors at the bases of the transistors, ground connecting each of the transistors at the emitters of the transistors, inverters and second resistors connecting each of the transistors at the collectors of the transistors, the second resistors each connecting a voltage source, one of the transistors connecting at the collector of the transistor a second inverter, the second inverter connecting a flip-flop, and the flip-flop connecting a second voltage source. ] The interface board connects with an input/output interface card of a computer.

US Patent:

54183782, May 23, 1995

Filed:

Mar 14, 1994

Appl. No.:

8/212247

Inventors:

Donald L. Friede - Austin TX
Van Le - Austin TX
Denver L. Dolman - Austin TX

Assignee:

Advanced Micro Devices - Sunnyvale CA

International Classification:

H01J 37302

US Classification:

25049221

Abstract:

An ion implanter is provided having a modulator which provides a variable frequency modulated scan signal. The modulator ensures that the scan signal will not retrace substantially upon itself during a scan cycle, and during subsequent scan cycles. Minimization of retrace allows for a more uniform dopant placed across the upper surface of the wafer and thereby eliminates or minimizes underdoping areas often arising between retraced beam widths when heavy atomic species are implanted.

US Patent:

20190058043, Feb 21, 2019

Filed:

Mar 30, 2016

Appl. No.:

16/080101

Inventors:

- Santa Clara CA, US
Rafael Rios - Austin TX, US
Shriram Shivaraman - Hillsboro OR, US
Marko Radosavljevic - Portland OR, US
Kent E. Millard - Hillsboro OR, US
Marc C. French - Forest Grove OR, US
Van H. Le - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/40
H01L 29/221
H01L 29/423
H01L 29/417
H01L 29/66
H01L 29/78

Abstract:

Disclosed herein are transistor gate-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material, a high-k dielectric disposed between the gate electrode material and the channel material, and indium gallium zinc oxide (IGZO) disposed between the high-k dielectric material and the channel material.

US Patent:

20140175378, Jun 26, 2014

Filed:

Dec 20, 2012

Appl. No.:

13/722746

Inventors:

Niti Goel - Austin TX, US
Niloy Mukherjee - Beaverton OR, US
Seung Hoon Sung - Beaverton OR, US
Van Le - Beaverton OR, US
Matthew Metz - Portland OR, US
Jack Kavalieros - Portland OR, US
RAVI PILLARISETTY - Portland OR, US
Sanaz Gardner - Portland OR, US
SANSAPTAK DASGUPTA - Hillsboro OR, US
Willy Rachmady - Beaverton OR, US
BENJAMIN CHU-KUNG - Hillsboro OR, US
MARKO RADOSAVLJEVIC - Beaverton OR, US
Gilbert Dewey - Hillsboro OR, US
Marc French - Hillsboro OR, US
JESSICA KACHIAN - Portland OR, US
SATYARTH SURI - Hillsboro OR, US
Robert Chau - Portland OR, US

International Classification:

H01L 21/20
H01L 21/764

US Classification:

257 15

Abstract:

An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.